Note that the clocks above apply to the U3 hardware revision 1.21. With hardware revision 1.20
all clocks are half of those values.
The same clock applies to all timers, so all 8-bit PWM channels will have the same frequency
and will have their falling edges at the same time.
PWM output starts by setting the digital line to output-low for the specified amount of time. The
output does not necessarily start instantly, but rather waits for the internal clock to roll. For
example, if the PWM frequency is 100 Hz, that means the period is 10 milliseconds, and thus
after the command is received by the device it could be anywhere from 0 to 10 milliseconds
before the start of the PWM output.
2.9.1.3 Period Measurement (32-Bit, Modes 2 & 3)
Mode 2: On every rising edge seen by the external pin, this mode records the number of clock
cycles (clock frequency determined by TimerClockBase/TimerClockDivisor) between this rising
edge and the previous rising edge. The value is updated on every rising edge, so a read
returns the time between the most recent pair of rising edges.
In this 32-bit mode, the processor must jump to an interrupt service routine to record the time,
so small errors can occur if another interrupt is already in progress. The possible error sources
are:
• Other edge interrupt timer modes (2/3/4/5/8/9/12/13). If an interrupt is already being
handled due to an edge on the other timer, delays of a few microseconds are possible.
• If a stream is in progress, every sample is acquired in a high-priority interrupt. These
interrupts could cause delays on the order of 10 microseconds.
• The always active U3 system timer causes an interrupt 61 times per second. If this
interrupt happens to be in progress when the edge occurs, a delay of about 1
microsecond is possible. If the software watchdog is enabled, the system timer interrupt
takes longer to execute and a delay of a few microseconds is possible.
Note that the minimum measurable period is limited by the edge rate limit discussed in Section
2.9.2.
Writing a value of zero to the timer performs a reset. After reset, a read of the timer value will
return zero until a new edge is detected. If a timer is reset and read in the same function call,
the read returns the value just before the reset.
Mode 3 is the same except that falling edges are used instead of rising edges.
2.9.1.4 Duty Cycle Measurement (Mode 4)
Records the high and low time of a signal on the external pin, which provides the duty cycle,
pulse width, and period of the signal. Returns 4 bytes, where the first two bytes (least
significant word or LSW) are a 16-bit value representing the number of clock ticks during the
high signal, and the second two bytes (most significant word or MSW) are a 16-bit value
representing the number of clock ticks during the low signal. The clock frequency is determined
by TimerClockBase/TimerClockDivisor.
The appropriate value is updated on every edge, so a read returns the most recent high/low
times. Note that a duty cycle of 0% or 100% does not have any edges.
To select a clock frequency, consider the longest expected high or low time, and set the clock
frequency such that the 16-bit registers will not overflow.
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