Matrox Solios eV-CL - Page 109

Connectors on Matrox Solios eV-CLBL and Matrox Solios eV-CLFL boards 109
Pin Hardware signal name MIL constant for
auxiliary signal
*
Digitizer device
number for
auxiliary signal
Description
2+,1- P0_LVDS_AUX_IN0 M_AUX_IO10 M_DEV0 LVDS auxiliary signal (input) for acquisition path 0,
which supports: trigger input (trigger controller 0 on acq
path 0), user input, field polarity input, or quadrature
input bit 0.
3+,6- P0_OPTO_AUX_IN0 M_AUX_IO6 M_DEV0 Opto-isolated auxiliary signal (input) for acquisition path
0, which supports: trigger input (trigger controller 0 on
acq path 0), user input, or field polarity input.
4 GND Ground.
5 TT L_AUX_IO_0 M_AUX_IO2 M _DEV 0/M _DEV 1 TTL auxiliary signal (input/ output), shared between both
acquisition paths for trig ger input (trigger controller 2 on
acq path 0; 2 on acq path 1), user input, or user out put
(M_USER_BIT4), and dedicated to acquisition path 0 for
timer output (M_TIMER2 on M _DEV 0).
8+,7- P0_LVDS_AUX_OUT0 M_AUX_IO12 M_DEV0 LVDS auxiliary signal (output) for acquisition path 0,
which supports: timer output (M_TIMER1 on M_DEV0)
or user output (M_USER_BIT0).
10+,9- P0_LVDS_AUX_IN1 M_AUX_IO11 M_DEV0 LVDS auxiliary signal (input) for acquisition path 0,
which supports: trigger input (trigger controller 1 on acq
path 0), user input, ti mer clock in put, or quadratur e inpu t
bit 1.
11 P0_TTL_AUX_IO_1 M_AUX_IO9 M_DEV0 TTL auxiliary signal (input/output) for acquisition path 0,
which supports: ti mer output (M_TIMER1/M_TIMER4 on
M_DEV0), trigger input (trigger controller 1 on acq path
0), user input, or user output (M_USER_BIT3).
12 GND Ground.
13 P0_TTL_AUX_IO_0 M_AUX_IO8 M_DEV0 TTL auxiliary signal (input/output) for acquisition path 0,
which supports: timer output (M_TIMER3 on M_DEV0),
trigger input (trigger controller 0 on acq path 0), user
input, user output (M_USER_BIT2), or field polarity
input.
14+,15- P0_OPTO_AUX_IN1 M_AUX_IO7 M_DEV0 Opto-isolated auxiliary signal (input) for acquisition path
0, which supports: trigger input (trigger controller 1 on
acq path 0) or user input.
16 NC Not connected.
18+,17- LVDS_AUX_IN0 M_AUX_IO4 M_DEV0/M_DEV1 LVDS auxiliary signal (input), shared between both
acquisition paths for trig ger input (trigger controller 2 on
acq path 0; 2 or 0 on acq path 1) or user input, and
dedicated to acquisition path 1 for field polarity input, or
quadrature input bit 0.