Matrox Solios eV-CL - Page 11

Matrox Solios eV-CL boards 11
The following flow diagram shows Matrox Solios eV-CLB in single-Medium
configuration.
PSG
Camera Link
Connector 0
(mini HDR-26)
ChannelLink
Receiver #1
Clock
Data (24)
& Syncs (4)*
SerTFG
SerTC
Camera Link
connector 1
(mini HDR-26)
24
UART
LVDS
transceivers
OptoAux (2)
External Auxiliary
I/O connector 0
(DBHD-15)
TTL buffers
Aux In (2)
Aux Out (1)
Optocoupler
Aux I/Os (3)
External Auxiliary
I/O connector 1
(DBHD-15 or DB-9)**
LVDS
transceivers
OptoAux (2)
TTL buffers
Aux In (2)
Optocoupler
Aux I/Os (1)
Cam Ctrl (4)
LVDS
drivers
LVDS driver
& receiver
LUTs
64
64
(up to 860 MB/s)
PCI-X to PCIe
Bridge
Host PCIe bus
ChannelLink
Receiver #2
Clock
Data (24)*
& Syncs (4)
28
Demultiplexer
Matrox Solios eV-CLB
single-Medium configuration
On a separate bracket.
28 bits serialized across 4 LVDS pairs. *
**
x4 PCIe
(Up to 1 GB/s)
MIL license
fingerprint
and
Supplemental MIL
license storage
32 DDR2
(up to 1.73 GB/s)
Acquisition
memory
(128/256/512 MB)
Acquisition
Controller
Video
Formatter
Color space
Converter
Bayer
converter