Matrox Solios eV-CL - Page 13

Matrox Solios eV-CL boards 13
Matrox Solios eV-CLF
Matrox Solios eV-CLF and eV-CLFL support acquisition from one Camera Link
device in single-Medium or single-Full configuration (with up to 10 taps). Matrox
Solios eV-CLF and eV-CLFL support Camera Link frequencies of up to 85 MHz.
Note that when using a 10 tap 8-bit video source, the maximum Camera Link
frequency is 70 MHz when grabbing to Host and 80 MHz when grabbing
on-board.
The following flow diagram shows Matrox Solios eV-CLF in single-Medium and
single-Full configuration.
PSG
Camera Link
Connector 0
(mini HDR-26)
ChannelLink
Receiver #1
Clock
Data (24)
& Syncs (4)*
SerTFG
SerTC
Camera Link
connector 1
(mini HDR-26)
24
UART
LVDS
transceivers
OptoAux (2)
External Auxiliary
I/O connector 0
(DBHD-15)
TTL buffers
Aux In (2)
Aux Out (1)
Optocoupler
Aux I/Os (3)
External Auxiliary
I/O connector 1
(DBHD-15 or DB-9)**
LVDS
transceivers
OptoAux (2)
TTL buffers
Aux In (2)
Optocoupler
Aux I/Os (1)
Cam Ctrl (4)
LVDS
drivers
LVDS driver
& receiver
LUTs
64
64
(up to 860 MB/s)
PCI-X to PCIe
Bridge
Host PCIe bus
ChannelLink
Receiver #2
Clock
Data (28)*
28
ChannelLink
Receiver #3
Clock
Data (28)*
28
Demultiplexer
On a separate bracket.
28 bits serialized across 4 LVDS pairs. In single-Medium mode,
ChannelLink Receiver #2 can only receive 24 bits of data and
ChannelLink Receiver #3 is not used.
*
**
x4 PCIe
(Up to 1 GB/s)
MIL license
fingerprint
and
Supplemental MIL
license storage
32 DDR2
(up to 1.73 GB/s)
Acquisition
memory
(128/256/512 MB)
Color space
converter
Video
Formatter
Acquisition
Controller
Matrox Solios eV-CLF