Matrox Solios eV-CL - Page 9

Matrox Solios eV-CL boards 9
The following flow diagram shows Matrox Solios eV-CLB in dual-Base
configuration.
PSG #0
PSG #1
Camera Link
Connector 0
(mini HDR-26)
ChannelLink
Receiver #1
Clock
Data (24)
& Syncs (4)*
SerTFG
SerTC
SerTFG
SerTC
Camera Link
connector 1
(mini HDR-26)
24
UART
UART
LVDS
transceivers
OptoAux (2)
External Auxiliary
I/O connector 0
(DBHD-15)
External Auxiliary
I/O connector 1
(DBHD-15 or DB-9)**
TTL buffers
Aux In (2)
Aux Out (1)
Optocoupler
Aux I/Os (3)
LVDS
transceivers
OptoAux (2)
TTL buffers
Aux In (2)
Aux Out (1)
Optocoupler
Aux I/Os (3)
ChannelLink
Receiver #2
Clock
Data (24)
& Syncs (4)*
24
LUTs
LUTs
32
32
Cam Ctrl (4)
Cam Ctrl (4)
LVDS
drivers
LVDS
drivers
LVDS driver
& receiver
LVDS driver
& receiver
32 DDR2
(up to 1.73 GB/s)
64
(up to 860 MB/s)
PCI-X to PCIe
Bridge
Host PCIe bus
Demultiplexer
Demultiplexer
Matrox Solios eV-CLB
dual-Base configuration
Acquisition
memory
(128/256/512 MB)
On a separate bracket.
28 bits serialized across 4 LVDS pairs.*
**
x4 PCIe
(Up to 1 GB/s)
Acquisition
Controller
MIL license
fingerprint
and
Supplemental MIL
license storage
Video
Formatter
Color space
Converter
Bayer
converter