Matrox Solios eV-CL - Page 97

Connectors on Matrox Solios eV-CLBL and Matrox Solios eV-CLFL boards 97
Pin Hardware signal name MIL constant for
auxiliary signal
*
Digitizer device
number for
auxiliary signal
Description
1 P1_TTL_AUX_IO_1 M_AUX_IO9 M_DEV1 TTL auxiliary signal (input/output) for acquisition path 1,
which supports: timer output (M_TIMER1 on M_DEV1),
trigger in put (tri gge r controller 1 on acq path 1), use r i nput,
or user output (M_USER_BIT3).
2+,17- P1_LVDS_AUX_OUT1 M_AUX_IO13 M_DEV1 LVDS auxiliary signal (output) for acqui sition path 1, which
supports: timer output (M_TIMER2 on M_DEV1) or user
output (M_USER_BIT 1).
5 P1_LVDS_HSYNC_OUT- HSYNC output for acq. path 1 (negative).
See pin 6 for more information.
6 P1_LVDS_HSYNC_OUT+ HSYNC output for acq. path 1 (positive).
7 P1_LVDS_CLK_OUT+ Clock output for acq. path 1 (positive).
9 NC Not connected.
10 NC Not connected.
11 P0_LVDS_CLK_OUT+ Clock output for acq. path 0 (positive).
12+,28- LVDS_AUX_IN1 M_AUX_IO5 M_DEV0/M_DEV1 LVDS auxiliary signal (input), shared between both
acquisition paths for trigger input (trigger controller 3 on
acq path 0; 3 or 1 on acq path 1) or user input, and
dedicated to acquisition path 1 for timer clock input or
quadrature in put bit 1.
13 P0_TTL_AUX_IO_1 M_AUX_IO9 M_DEV0 TTL auxiliary signal (input/output) for acquisition path 0,
which supports: timer output (M_TIMER1/M_TIMER4 on
M_DEV0), trigger inpu t (trig ger controller 1 on acq path 0),
user input, or user out put (M _USER_BIT 3).
14 GND Ground.
15 TTL_AUX_IO_1 M_AUX_IO3 M_DEV0/M_DEV1 TTL auxiliary signal (input/output), shared between both
acquisition paths for trigger input (trigger controller 3 on
acq path 0; 3 on acq path 1), user input, or user output
(M_USER_BIT5), and dedicated to acquisition path 1 for
timer output (M_TIM ER 2 on M _D EV 1).
16 GND Ground.
19+,3- P0_LVDS_AUX_OUT1 M_AUX_IO13 M_DEV0 LVDS auxiliary signal (output) for acquisition path 0, which
supports: timer output (M_TIMER2 on M_DEV0) or user
output (M_USER_BIT 1).
20+,4- P0_LVDS_AUX_OUT0 M_AUX_IO12 M_DEV0 LVDS auxiliary signal (output) for acquisition path 0, which
supports: timer output (M_TIMER1 on M_DEV0) or user
output (M_USER_BIT 0).
21 P1_LVDS_VSYNC_OUT- VSYNC output for acq. path 1 (negative).
See pin 36 for more information.