RESERVED (0x6) ........................................................................41
Clock Configuration 1 (0x7) .................................................................42
Test Mode 1 (0x8) ........................................................................43
Test Mode 2 (0x9) ........................................................................44
Clock Configuration 2 (0xA).................................................................45
Applications Information........................................................................ 46
IF Filter Center Frequency Configuration .........................................................46
Operation for Wideband Signals................................................................46
Determining AGC Gain Setpoint ................................................................47
PCB Layout Considerations ...................................................................47
Power-Supply Layout ........................................................................47
Typical Application Circuit ...................................................................... 48
Circuit 1 ...................................................................................48
External Component List .....................................................................49
Ordering Information .......................................................................... 49
Revision History .............................................................................. 50
Figure 1. ADC Quantization Levels for 2 and 3-Bit Cases ............................................. 21
Figure 2. DSP Interface Top Level Connectivity and Control Signals ..................................... 23
Figure 3. Clock Distribution ..................................................................... 24
Figure 4. Register Read Functional Timing ......................................................... 26
Figure 5. Register Write Functional Timing ......................................................... 26
Figure 6. Three-Wire Interface Timing Diagram ..................................................... 27
TABLE OF CONTENTS
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CONTINUED
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LIST OF FIGURES
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MAX2771 Multiband Universal GNSS Receiver
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