Microhard Systems IP-921 - Page 172

© Microhard Systems Inc. CONFIDENTIAL 172
IP9xx Series
Appendix G: SIP Interface Schematic (Page 2)
TG2 TARGET
TG1 TARGET
Size Drawn By :
CAGE Code
DWG NO
Rev
Sheet
of
Checked By:
Approved:
Detail:
0
Microhard Systems Inc.
<Doc>
Tuesday, February 12, 2008
2 2
B
17, 2135-32 Av e NE Calgary , Alberta, Canada T2E 7P1
SIP Interface board
<Cage Code>
Interface2
H. Shenouda
H. Shenouda
+3V3 Driv ers
R25 10k
DDDDDD
D
D
D
D
D
+3V3 Driv ers
D
D
D
D
D
M1 MT HOLE
1
DD
M2 MT HOLE
1
D
M4 MT HOLE
1
M3 MT HOLE
1
D
mhx_LED2 mhx_LED1
mhx_LED_RX mhx_LED_TX
mhx_LED3
D10
GRN LED
1 2
D11
GRN LED
1 2
D9
GRN LED
1 2
R121 150R R120 150R
D7
GRN LED
1 2
R119 150R
D6
RED LED
1 2
R124 150R R123 150R
CPU_Status
D8
GRN LED
1 2
R122 150R
+3V3 Driv ers
1
3
2
D14 SM712-2
D
RX+
TX+ RX-
TX-
+3V3 Driv ers
U1
max3491
GND
6
RD
2
D+
9
RE
3
DE
4
DI
5
GND
7
NC
8
NC
1
D-
10
R-
11
R+
12
Vcc
14
Vcc
13
C1
0.47uF
D
1
3
2
D15 SM712-2
+3V3 Driv ers
TXD0_i DE_485
D
D
R130 10k
R129 10k
RxD0_i_485
!RE_485
+3V3 Driv ers
D
+3V3 FPGA
S1
TL1105PF
1
2
3
4
+3V3 Driv ers
+
C186 4.7uF
12
VRF
U21 LP2980AIM5-3.3
IN
1
OUT
5
EN
3
GND
2
NC
4
D
D
!RSMode
C18
0.47uF
U4 MAX3245
Rout2A
20
C2+
1
!Inv alid
21
V-
3
C2-
2
!Forceoff
22
Din1
14
Din2
13
Din3
12
Rout1
19
Rout2
18
Rout3
17
Rout4
16
Rout5
15
Rin5
8
Rin4
7
Rin3
6
Rin2
5
Rin1
4
Dout3
11
Dout2
10
Dout1
9
Forceon
23
C1-
24
GND
25
V+
27
Vcc
26
C1+
28
C15 0.47uF
C7
0.47uF
C16
0.47uF
C10 0.47uF
RXD0 TXD0 DCD0 RTS0
TXD0_i
DCD0_i
DTR0
!RxD0_i_232
RTS0_i
CTS0_i CTS0
DTR0_i
+
C6 4.7uF
12
!RSMode
U3 MAX3245
Rout2A
20
C2+
1
!Inv alid
21
V-
3
C2-
2
!Forceoff
22
Din1
14
Din2
13
Din3
12
Rout1
19
Rout2
18
Rout3
17
Rout4
16
Rout5
15
Rin5
8
Rin4
7
Rin3
6
Rin2
5
Rin1
4
Dout3
11
Dout2
10
Dout1
9
Forceon
23
C1-
24
GND
25
V+
27
Vcc
26
C1+
28
C17
0.47uF
C13 0.47uF
C5
0.47uF
C14
0.47uF
C9 0.47uF
Microhard Systems Inc. Confidential and Proprietary
RTS1
+3V3 Driv ers
CTS1 RXD1 TxD1 DSR0
RTS1_i
!USR_RESET_i
DSR0_i
CTS1_i
!RXD1_i
TxD1_i
!CONFIG