Microhard Systems IP-921 - Appendix G: SIP921 Customer Interface Schematic

© Microhard Systems Inc. CONFIDENTIAL 171
IP9xx Series
Appendix G: SIP Interface Schematic
Size Drawn By :
CAGE Code
DWG NO
Rev
Sheet
of
Checked By:
Approved:
Detail:
0
Microhard Systems Inc.
<Doc>
Tuesday, February 12, 2008
1 2
B
17, 2135-32 Av e NE Calgary , Alberta, Canada T2E 7P1
SIP Interface board
<Cage Code>
Connectors
H. Shenouda
H. Shenouda
TXD1 RXD1 RTS1
D
CTS1
J2
MOLEX Picoclasp 5013311007
1 2 3 4 5 6 7 8 9
10
DTR0 RXD0 TXD0 DCD0 CTS0 RTS0 DSR0
D
J3
MOLEX Microfit 0430450200
1 2
RI CTS TXD
+Vin
D
RTS DCD GND DTR DSR RXD
Serial Port
RX+ TX- TX+ RX-
Power Port
+3V3
R44
49.9
R41
49.9
R38
49.9
C8
1000p
R40
49.9
R39
49.9
R45
49.9
D
J1
TYCO406549-1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
+
14
-
13
+
16
-
15
CAT6
ACTIVITY LED
CAT1 CAT2 CAT3
LINK LED
Ethernet Port
JP5
HEADER 4
1 2 3 4
Diagnostics Port
JP1 80610
1 2 3 4 5 6 7 8 9
!RXD1_i
D
D
CTS0_i
!RE_485
DTR0_i
TXD1_i
DE_485
TXD0_i
DCD0_i
DSR0_i
CTS1_i RTS1_i
mhx_LED2
mhx_LED_RX
RTS0_i
CAT6
mhx_LED_TX
mhx_LED1 mhx_LED3
CAT1 CAT2CAT3
JP4
HEADER 26X2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5251
!CONFIG
+3V3
!RSMODE
RXD0_i_485
LINK LED ACTIVITY LED
+3V3 FPGA VRF
CPU_Status
D
+Vin
!RxD0_i_232
!USR_RESET_i
Microhard Systems Inc. Confidential and Proprietary