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LCD PC E
LCD PC E
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8590 MAINTENANCE
8590 MAINTENANCE
Flexible row and column addresses. 64-bit data width only
LVTTL 3.3V DRAM interface with 5V-tolerant inputs for SDR SDRAM and 2.5V SSTL-2 DRAM interface
for DDR SDRAM
Programmable I/O drive capability for MA, MD, and command signals
Dual copies of MA and control signals for improved drive
Optional ECC (single-bit error correction and multi-bit error detection ) or EC (error checking only) for DRAM
integrity
Two-bank interleaving for 16Mbit SDRAM support
Two-bank and four bank interleaving for 64Mb, 128Mb, 256Mb, 512Mb SDRAM support
Supports maximum 16-bank interleave (i.e., 16 pages open simultaneously); banks are allocated based on LRU
Seamless DRAM command scheduling for maximum DRAM bus utilization
- (e.g., precharge other banks while accessing the current bank)
Four cache lines (16 quad words) of CPU to DRAM write buffers
Four cache lines of CPU to DRAM read prefetch buffers
Read around write capability for non-stalled CPU read
Speculative DRAM read before snoop result
Burst read and write operation
Burst length 4 and 8 for SDR and DDR
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