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LCD PC E
LCD PC E
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8590 MAINTENANCE
8590 MAINTENANCE
Request / Data split transaction
Configurable outstanding transaction queue for Host to V-Link Client accesses
Supports Defer / Defer-Reply transactions
Transaction assurance for V-Link Host to Client access eliminates V-Link Host-Client Retry cycles
Intelligent V-Link transaction protocol to eliminate data wait-state / throttle transfer latency
All V-Link transactions for both Host and Client have a consistent view of transaction data depth and buffer size
to avoid data overflow
Highly efficient V-Link arbitration with minimum overhead
All V-Link transactions have predictable cycle length with known command / data duration
Advanced High-Performance DDR /SDR DRAM Controller
DRAM interface pseudo-synchronous with host CPU (100 MHz) for most flexible configuration
DRAM interface may be faster than CPU by 33 MHz to allow use of 133 MHz memory with 100 MHz FSB clock
Concurrent CPU, AGP, and V-Link access
Supports SDR and DDR SDRAM memory types
Clock Enable (CKE) control for SDRAM power reduction in high speed systems
Mixed 16M / 32M / 64M x 8/16/32 DRAMs
Supports 8 banks up to 4 GB DRAMs (512Mb x8/x16 DRAM technology )
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