MiTAC E-8590 - Page 41

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LCD PC E
LCD PC E
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8590 MAINTENANCE
8590 MAINTENANCE
Figure 1: System clock structure and ICS 950902 block diagram
PLL2
Block Diagram
48MHz
24_48MHz
REF1:0
1/2
X1
X2
PLL1
Spread
Spectrum
BUF_IN
SEL_40S/K7
RESET#
SEL_SD_DDR
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CLK_STOP#
MULTISEL0
Vtt_PWRGD#
MODE
CPUT_DDT
CPUC_CS
CPUT_CS
CPUCLKODC
DDRT( 5:0)
SDRAM(11,9,7,5,3,1)
PCICLK(5: 0)
PCICLK_F
AGPCLK(2:0)
RESET#
I REF
XTAL
OSC
CONTROL
LOGIC
CONFIG.
REG
SDRAM
DIVDER
PCI
DIVDER
Stop
Stop
Stop
CPU
DIVDER
DDR/SD
DIVDER
CPU
DIVDER
Stop