60
LCD PC E
LCD PC E
-
-
8590 MAINTENANCE
8590 MAINTENANCE
VDDSPD = +2.3V to +3.6V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; centeraligned with data for WRITEs
Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/received with data—i.e., source-synchronous data capture
Differential clock inputs (CK and CK#)
Four internal device banks for concurrent operation
Programmable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
15.6µs (256MB), 7.8125µs (512MB) maximum average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Programmable READ CAS latency
Gold-plated edge contacts
2 banks on one socket
Need damping resisters on data lines for better signal integrity
Max Address line: A0.. A12, BA0 BA1
To Next Page
Loading...