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CHAPTER 10 MULTIPLE CPU HIGH-SPEED
TRANSMISSION DEDICATED
INSTRUCTIONS
10.1 Overview
The multiple CPU high-speed transmission dedicated instruction directs the Universal model QCPU to write/read device data
to/from the Universal model QCPU in another CPU.
The following shows an operation when CPU No.1 writes device data to CPU No.2 with the multiple CPU high-speed
transmission dedicated instruction.
The multiple CPU high-speed transmission dedicated instruction in either host CPU or another CPU (target CPU module of
instruction) is available only for the following CPU modules.
• Q03UDCPU, Q04UDHCPU, Q06UDHCPU
The first five digits of serial numeber is 10012 or higer.
• Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Q26UDHCPU
•QnUDE (H) CPU
(1) Parameter setting and system configuration to execute the multiple CPU high-speed transmission dedicated instruction
The multiple CPU high-speed transmission dedicated instruction can be executed in the following parameter setting and
system configuration.
• CPU No.1 uses QnUD(H)CPU or QnUDE(H)CPU.
• The multiple CPU high speed main base unit (Q3 DB) is used.
• "Use multiple CPU high speed transmission" is selected in the Multiple CPU settings screen of PLC parameter.
CPU No.1
User program
DP.DDWR U3E1 D0 D100 D200 M0
D0
D100
D0
D200
CPU No.2
Writing
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