Use one of the following methods to access the user-defined FPGA signals in LabVIEW:
• Right-click your FPGA Target and select New»RIO Mezzanine Card... to choose a
generic Digital RMC and access all 96 DIO lines with digital I/O nodes.
Note This methodology does not allow you to configure the DIO lines as
processor peripherals such as CAN, SDIO, or Serial.
• 1. Right click your FPGA Target and select Launch sbRIO CLIP Generator... to
launch the NI Single-Board RIO CLIP Generator application, which you can use to
create a socketed component-level IP (CLIP) that defines the FPGA signals or
processor peripherals to use in your application.
2. After you create a CLIP, return to LabVIEW and right-click an RMC Socket under
the FPGA Target and select Properties.
3. In the Socket Properties dialog box, select your CLIP and click OK. The I/O appears
under the socket, or the I/O is connected directly to the RT processor.
Note For a given FPGA target, you must use either the digital I/O method or the
socketed CLIP method for all 96 DIO lines.
FPGA DIO
Figure 22. Circuitry of One 3.3 V DIO Channel on the RMC Connector
ZYNQ 7020 FPGA
RMC Connector
42.2 Ω
The RMC has a total of 96 DIO channels. The NI sbRIO device is tested with all DIO
channels driving ±3 mA DC loads. DIO signals are tristated (floating) before and during
FPGA configuration. After FPGA configuration completes, unused DIO signals remain
tristated. To ensure startup values, place pull-up or pull-down resistors on an RMC. The DIO
channels on the NI sbRIO device are routed with a 55 Ω characteristic trace impedance. Route
all RMCs with a similar impedance to ensure the best signal quality. Refer to 3.3 V Digital I/O
on RMC Connector section in the NI sbRIO-9607 Specifications on ni.com/manuals for the
logic levels.
Note Refer to the NI sbRIO-9607/9627 RMC Design Guide on ni.com/manuals for
information about FPGA DIO best practices.
FPGA DIO Clock Capabilities
• Single-region clock capable (SRCC)—These pins provide a direct connection to the
global clock distribution buffers in the FPGA. The pins also connect to the regional
buffers on a specific bank of pins. Each SRCC pin has an _SRCC suffix in the pin name.
• Multi-region clock capable (MRCC)—These pins provide a direct connection to the
global clock distribution buffers in the FPGA. The pins also connect to the regional and
40 | ni.com | NI sbRIO-9607 User Manual
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