has specific filtering requirements. The NI sbRIO-9607/9627 RMC Design Guide on ni.com/
manuals provides design guidelines, requirements for routing signals, requirements for the 5 V
filtering, and recommendations for an appropriate connector.
RMC RST#
The RST# pin indicates that power provided through the RMC Connector is valid or that the
sbRIO-9607 is in reset. The signal goes to 3.3 V if the power is valid when the board powers
up or when coming out of reset. The signal asserts to 0 V for at least 1 ms before returning to
3.3 V when going into reset. This includes the RMC Connector, traces, vias, and device pins.
Refer to the NI sbRIO-9607 Specifications on ni.com/manuals for output logic levels.
SYS RST#
The SYS_RST# signal is a system reset signal for resetting the sbRIO-9607 processor and
FPGA. Asserting this signal causes the RMC RST# signal to also assert. The SYS_RST#
signal asserts low.
The amount of time for which you assert this signal determines the specific reset behavior.
This behavior is the same as shown in the Reset Button Behavior section of this document.
You can assert the SYS_RST# signal before you apply power to the sbRIO-9607. The
sbRIO-9607 remains in reset until the SYS_RST# signal de-asserts. If you assert the
SYS_RST# signal before power is applied, then you must de-assert the SYS_RST# signal
within five seconds.
FPGA_CONF
The FPGA_CONF pin asserts high when the FPGA has been programmed. When the FPGA is
not configured the signal may be either floating or driven low. A pull-down resistor is required
when using this signal to ensure it returns to ground.
User-Defined FPGA Signals
The RMC connector provides FPGA Digital I/O (DIO) pins that you configure for purposes
specific to your application. You can use these signals to implement the following interfaces:
• FPGA DIO
• Additional UART (4 RS-232 and 2 RS-485) Support
• CAN Support
• SDIO Support
NI sbRIO-9607 User Manual | © National Instruments | 39
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