Quantum FIREBALL PLUS AS 10.2 User Manual

ATA Bus Interface and ATA Commands
Quantum Fireball Plus AS 10.2/20.5/30.0/40.0/60.0 GB AT 6-27
6.6.2.8
6.6.2.86.6.2.8
6.6.2.8 Status Register
Status RegisterStatus Register
Status Register
The Status Register contains information about the status of the drive and the
controller. The drive updates the contents of this register at the completion of each
command. When the Busy bit is set (BSY=1), no other bits in the Command Block
Registers are valid. When the Busy bit is not set (BSY=0), the information in the
Status Register and Command Block Registers is valid.
When an interrupt is pending, the drive considers that the host has acknowledged
the interrupt when it reads the Status Register. Therefore, whenever the host reads
this register, the drive clears any pending interrupt. Table 6-16 defines the Status
Register bits.
Table 6-16
Table 6-16 Table 6-16
Table 6-16
Status Register Bits
Note:
Note:Note:
Note: The content of # bit is command dependent.
Bits 2 and 1 are obsolete according to the ATA-4 specification.
MNEMONIC
MNEMONICMNEMONIC
MNEMONIC BIT
BITBIT
BIT DESCRIPTION
DESCRIPTIONDESCRIPTION
DESCRIPTION
BSY 7 Busy bit. Set by the controller logic of the drive whenever the
drive has access to and the host is locked out of the Command
Block Registers.
BSY is set under the following conditions:
• Within 400 ns after the deassertion of RESET- or after SRST is set in
the Device Control Register. Following a reset, BSY will be set for no
longer than 30 seconds.
• Within 400 ns of a host write to the Command Block Registers with
a Read, READ LONG, READ BUFFER, SEEK, RECALIBRATE, INITIALIZE
DRIVE PARAMETERS, Read Verify, Identify Drive, or EXECUTE DRIVE
DIAGNOSTIC command.
• Within 5 µsec after the transfer of 512 bytes of data during the
execution of a Write, Format Track, or WRITE BUFFER command, or
512 bytes of data and the appropriate number of ECC bytes during
the execution of a WRITE LONG command.
When BSY=1, the host cannot write to a Command Block Register
and reading any Command Block Register returns the contents of the
Status Register.
DRDY 6 Drive Ready bit. Indicates that the drive is ready to accept a
command. When an error occurs, this bit remains unchanged until
the host reads the Status Register, then again indicates that the drive
is ready. At power on, this bit should be cleared, and should remain
cleared until the drive is up to speed and ready to accept a command.
#5
#4
DRQ 3 Data Request bit. When set, this bit indicates that the drive is ready to
transfer a word or byte of data from the host to the data port.
Obsolete 2
Obsolete 1
ERR 0 Error bit. When set, this bit indicates that the previous command
resulted in an error. The other bits in the Status Register and the bits
in the Error Register contain additional information about the cause
of the error.

Quantum FIREBALL PLUS AS 10.2 Specifications

General

Brand	Quantum
Model	FIREBALL PLUS AS 10.2
Category	Storage
Language	English