Renesas RZ/A Series - Memory; Sdram

RZ/A2M SUB Board RTK79210XXB00000BE 2. Function specifications
R20UT4398EJ0100 Rev.1.00 2-19
2018.10.11
2.3 Memory
2.3.1 SDRAM
The RTK79210XXB00000BE is equipped with external SDRAM×1 shown in Table 2.3.1 as the standard
configuration. SDRAM control is performed by the RZ/A2M on-chip bus state controller (BSC). There is a 16-bit
connection to the SDRAM.
Figure 2.3.1 shows the SDRAM block diagram, and Table 2.3.2 shows the function settings of the DIP switch SW6-1
for system settings. Table 2.3.3 shows clock pulse oscillator settings, and Table 2.3.4 and Table 2.3.5 show the RZ/A2M
bus state controller settings (read and write for SDRAM) when the bus clock is operating at 132MHz.
Table 2.3.1 SDRAM Overview
Specifications
Details
Model name
IS42S16320F-7TL
Configuration
64 MBytes (8 Mwords x 16 bits x 4 banks) x 1
Capacity
64 MBytes
Access time
5.4 ns
CAS latency
3 (when system clock is 132 MHz)
Refresh interval
8192 refresh cycle every 64 ms
Row address
A12 to A0
Column address
A9 to A0
Number of banks
4-bank operation controlled by BA0 and BA1