- 89 -
Control Port Functions
Pin Function Name Function Pol. Action
132 GND Power for Input/Output(0V) - -
133 CS_SDI_CPU Dual SDI Control(4 line Serial SOUT)
134 3.3V Power for Input/Output(3.3V) - -
135 SCLK_GAM_CPU Control for Digital Gamma IC (3 line Serial CLK)
136 SDATA_GAM_CPU Control for Digital Gamma IC (3 line Serial DATA)
137 GND Power (0V) - -
138 SCALER_RESET SCALER Reset Signal O Reset with H->L->H
139 1.9V Power (1.9V) - -
140 PW_SEL PIXEL 232C Selection O SH:H, PW:L
141 EXP_RESET I/O Expander-1/2 Reset SIgnal O Reset: H
142 NET_SW O
143 TDO [for ICE] Test Data output O -
144 (Not used) PCC Reset/DMA Request - (Open)
145 (Not used) PCC Buffer Control/DMA acknowledge0 - (Open)
146 SAM3_WAIT Hardware Wait Request I Wait with L
147 RESETM Manual Reset Reuest I -
148 Reserved Analog Trigger/Inout Port H (Open)
149 SIN_SDI_CPU Dual SDI Control (4 line Serial SIN) I Not used
150 ASEMD0 [for ICE] ASE Mode I -
151 ASEBRKAK [for ICE] ASE Brake O -
152 USBB VBUS USB Connection Check I -
153 AUDATA[3] [for ICE] AUD data O -
154 AUDATA[2] [for ICE] AUD data O -
155 GND Power (0V) - -
156 AUDATA[1] [for ICE] AUD data O -
157 1.9V Power (1.9V) - -
158 AUDATA[0] [for ICE] AUD data O -
159 GND Power for Inout/Output(0V) - -
160 TRST [for ICE] Teset Reset I -
161 3.3V Power for Inout/Output(3.3V) - -
162 TMS [for ICE] Test Mode Switch I -
163 TDI [for ICE] Test Data Input I -
164 TCK [for ICE] test Clock I -
165 (Not used) I -
166 --- PCCREG/Input Port F/Reserved I (Open)
167 LAMP1_ERR Lamp1 Fail Detection I Lamp Failure Detection until Dimmer Starts
168 LAMP2_ERR Lamp2 Fail Detection I Lamp Failure Detection until Dimmer Starts
169 MD0 Clock Mode Setting [Default:L] I Switch
170 1.9V PLL1 Power (1.9V) - -
171 CAP1 PLL1 External Condenser - [470pF]
172 GND PLL1 Power (0V) - -
173 GND PLL2 Power (0V) - -
174 CAP2 PLL2 External Condenser - [470pF]
175 1.9V PLL2 Power (1.9V) - -
176 AUDCK [for ICE] AUD Clock I -
177 GND Power (0V) - -
178 1.9V Power (1.9V) - -
179 Reserved Clock Oscillator - (Open)
180 EXTAL Extarnal Click/X’TAL I -
181 Not used (Input Port) I
182 Not used (Input Port) I -
183 FPGA_nSTATUS Error Detection during the Configuration I H:Error
184 FPGA_CONF_DONE OK Detection during the Configuration I H:OK
185 SDA_AV IIC Bus IO LActive
186 SCL_AV IIC Bus IO LActive
187 LCD Clock Output/InputOutput Port H IO -
188 GND Power for Inout/Output(0V) - -
189 CKIO System Clock IO I/O -
190 3.3V Power for Inout/Output(3.3V) - -
191 TxD0 Transmitting Data0 [PADremote Control] O
192 (Not used) Serial Clock0/IO Port for SCI - (Open)
193 (Not used) SIOF Send Data/Output Port for SCI - (Open)
194 (Not used) SIOF Clock In/IO Port for SCI - (Pull-up)
195 TxD2 Send Data2 [External] O 19200bps or 9600bps
196 (Not used) SIOF Clock/IO Port for SCI - (Pull-up)
197 (Not used) SIOF Frame Sync/IO Port for SCI - (Pull-up)
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