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Schweitzer Engineering Laboratories SEL-700G1 - Page 8

Schweitzer Engineering Laboratories SEL-700G1
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vi List of Tables
SEL-700G Relay Instruction Manual Date Code 20170814
Table 4.26 Equations Associated With IEC Curves...............................................................................4.98
Table 4.27 Available Ground Directional Elements............................................................................. 4.103
Table 4.28 Best Choice Ground Directional Element Logic................................................................ 4.104
Table 4.29 Ground Directional Element Availability by Voltage Transformer Connections
On X Side .......................................................................................................................4.104
Table 4.30 Ground Directional Element Availability by Voltage Transformer Connections
On Y Side .......................................................................................................................4.105
Table 4.31 Directional Element Settings for X Side and Y Side ......................................................... 4.121
Table 4.32 Directional Control Settings Not Made for Particular Conditions.....................................4.124
Table 4.33 Overcurrent Elements Controlled by Level Direction Settings
DIR1X, DIR2X, DIR1Y, and DIR2Y
,
............................................................................. 4.124
Table 4.34 Relay Word Bits Associated With X-Side and Y-Side Overcurrent Elements
With and Without Directional Control Across Different SEL-700G Models ................4.124
Table 4.35 z Constant for Z2R Setting................................................................................................. 4.127
Table 4.36 z Constant for Z0R Setting................................................................................................. 4.130
Table 4.37 Load-Encroachment Settings .............................................................................................4.134
Table 4.38 Power Element Settings...................................................................................................... 4.138
Table 4.39 Signals Used for Frequency Measurement and Tracking................................................... 4.141
Table 4.40 Frequency Settings ............................................................................................................. 4.142
Table 4.41 Rate-of-Change-of-Frequency Settings.............................................................................. 4.143
Table 4.42 Time Window Versus 81RmnTP Setting............................................................................4.144
Table 4.43 Undervoltage Settings ........................................................................................................ 4.146
Table 4.44 Overvoltage Settings ..........................................................................................................4.147
Table 4.45 RTD Settings ...................................................................................................................... 4.150
Table 4.46 RTD Resistance Versus Temperature.................................................................................4.152
Table 4.47 X-Side Synchronism-Check Settings................................................................................. 4.153
Table 4.48 Synchronism-Check Settings .............................................................................................4.167
Table 4.49 Autosynchronism Settings.................................................................................................. 4.174
Table 4.50 Loss of Potential (LOP) Settings........................................................................................ 4.179
Table 4.51 Demand Meter Settings...................................................................................................... 4.180
Table 4.52 Pole Open Logic Settings...................................................................................................4.185
Table 4.53 Trip/Close Logic Settings................................................................................................... 4.186
Table 4.54 Enable Settings................................................................................................................... 4.193
Table 4.55 Latch Bits Equation Settings.............................................................................................. 4.195
Table 4.56 SEL
OGIC Control Equation Operators (Listed in Operator Precedence) .................................4.197
Table 4.57 Other SEL
OGIC Control Equation Operators/Values.......................................................... 4.200
Table 4.58 SEL
OGIC Variable Settings................................................................................................. 4.201
Table 4.59 Counter Input/Output Description...................................................................................... 4.203
Table 4.60 Order of Precedence of the Control Inputs......................................................................... 4.204
Table 4.61 Control Output Equations and Contact Behavior Settings.................................................4.205
Table 4.62 General Global Settings ..................................................................................................... 4.206
Table 4.63 Event Messenger Settings .................................................................................................. 4.206
Table 4.64 Setting Group Selection .....................................................................................................4.208
Table 4.65 Time and Date Management Settings ................................................................................4.208
Table 4.66 Breaker Failure Setting....................................................................................................... 4.211
Table 4.67 Summary of Steps ..............................................................................................................4.213
Table 4.68 Analog Input Card in Slot 3 ............................................................................................... 4.215
Table 4.69 Output Setting for a Card in Slot 3.....................................................................................4.216
Table 4.70 Slot C Input Debounce Settings .........................................................................................4.218
Table 4.71 Data Reset Settings.............................................................................................................4.218
Table 4.72 Setting Change Disable Setting.......................................................................................... 4.219
Table 4.73 Time Synchronization Source Setting................................................................................4.219
Table 4.74 Front-Panel Serial Port Settings......................................................................................... 4.220
Table 4.75 Ethernet Port Settings......................................................................................................... 4.220
Table 4.76 Port Number Settings That Must be Unique......................................................................4.221
Table 4.77 Fiber-Optic Serial Port Settings .........................................................................................4.221
Table 4.78 Rear-Panel Serial Port (EIA-232) Settings......................................................................... 4.221
Table 4.79 Rear-Panel Serial Port (EIA-232/EIA-485) Settings.......................................................... 4.222

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