PC-1600
UART
R S·232C interface
Receive
data
At the same time the RS-232C interface is selected with a
high PRIME state, VDD is supplied from the high side of
the RS-232C interface.
The SIO interface is selected with a low PRIME state and
VDD is turned off. During the system on and reset, PRIME
is at low.
PRIME
------------------~
SO F (0_!_jIJJJJJ[j
~====--------------------------
ROF (I)
murrrn
~~L_ __
TXO (0) -- -- --- - -- - - -- -
_n_,
rm:rr:rnn
RX 0
(I)
n -- - -- - - -- -- - -- - -- -,
rrnmunLU..Ll.ll.U.L___
-;:::=========
RTS (0)
CTS(I)
CO
(I)
OSR
(I)
Cf
(I)
OTR (0)
v
00 - - - - - - - - - - - - - - - - - - - - -
TXO(UAR~
ummrn
RXO (UARTJ
UIIIIIIII lIIIIIllIII
CD
When PR IME is at a low state, the RS-232C interface
outputs
either in a high impedance or a low
state
(non-
active).
® When PRIME is at a low state, the SIO interface
1/0
signals, SDF and RDF, are in an opposite polarity with
the UART
Input/output
signals, TXD and RXD. The
start bit is high and the stop bit is low. So, both are
in a low state when no data are sent or received (UART
TXD and RXD are at a high level).
® When PRIME is at a high state, both SDF and RDF are
at a low level and non-active (stop bit}.
@ When PRIME is at a high state, TXD and RXD of the
RS-232C interface are opposite in their
polaritv
as are
those of TXD and RXD of the UART.
@ When PRIME goes high, VDD is activated (RS-232C
interface high side voltage),
® The RS·232C interface
input/output
signals-CTS,
DSR, CD, and CI-are
Input
to the UART (opposite
polarity), regardless of the state of PRIME (high or
low),
7-7-1. RS·232C interface signal
Although signals of this interface conform to the EIA
standards, they are used for controls that differ in some
ways from the RS-232C interface in general.
-14-
(1) Input signals are received by the transistor and are
output
through the open collector and pulled up
to VCC using a resistor, as shown in the hybrid
IC BX7269W. A diode is inserted across the base and
emitter of the input which will bring the signal below
the GND level (stop
bit,
etc.) and make it assume to
be at the GND level. Therefore, the input signal is
converted in the hybrid IC to be handled as a logic
signal.
GND
0 I
__jU
- __ Vcc
~-GND
-
(2) On the other hand, the
output
signal is
output
through the circuit shown below (hybrid IC),
While the input level is CMOS compatible (0-4.7V),
the
output
is converted to the VDD-VEE level.
The figure below illustrates this.
Va
Vcc
GND
Vb
VDD_j\
Vcc
00-
::: : :::-c- __:-~:-~-=~~-::-~--~-~-~------~--~-~-V
y,""
n n n
Vc
::l I
VEE
CD
When the input (a) is low (GND), the level (b) is below
GND and is assumed by the MN4584 to be at a low
level.
The MN4584 IC is a Schmitt inverter to which VDD
and VEE is supplied. This IC has a hvsteresis against
input.
Output
VEE VTHL GND VnlH VDD
Input
To Next Page
Loading...
