Sharp PC-1600

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PC-1600
9. LSI pin descriptions
• SC7852 (main CPU 1)
• LH5803 (main CPU 2)
• LU57813P (sub CPU)
• LR38041 (gate array)
• TC8576F (UART)
9-1. Main CPU 2 (SC7852) pin description
Pin
Symbol
ln/Out
Active
Function
No. level
95~
KINO~KIN7
vln Low
(1)
Internally pulied up to VCC bv the resistor (200K ~ 5000K).
100~2
(2)
T input > Low (normal mode) keyboard Input.
A key in the low input line is pressed.
(3)
T input r= High (emulation mode).
Usedfor connection of the Z-80 ICE.
3
LHWAIT Out High Wait output to the LH-5803.
The signal goeshigh in one of the following:
(1)
When the WAIT input is at a high level.
(2)
When the LH-5803 accesses**O*H or 8000H ~ FFFFH of the ME1 space, it goes
high for one cycle time to insert one wait.
(3)
When the Z-80 is running with the LH-5803 at halt.
4 q,OS
In
J1I'
LH-5803 basicclock (1.3MHz).
This clock isused for the sync signal of the internal LH-5810 corresponding port and
generation of the LCD CLOCK (217KHz).
5 PT Out Memory bank signal.
6
PU
Out Memory bank signal.
7
PVOUT
Out
Memory bank signal.
8
PVIN
""In
LH-5803's PV signal input.
As PV is kept in the floating state when the Z-80 is operating, it is internally pulled
down by the resistor.
9
WR
ln/Out
Low
(1 )
When the Z-80 is in operation, the Z-80's WR is a direct output on this line.
(2)
Whenthe LH-5803 is in operation, it becomesan Input to enable R/W for
the LH-5803.
10~25 A15~AO
"" ln/Out
(1) When the Z-80 is in operation, the Z-80 addressbus is an output on this line.
(2)
When the LH-5803 is in operanon. the LH-5803 addressbus isan Input on this line.
26~33
DB7~DBO
ln/Out Data bus.
34 10RQ
"" ln/Out
(1)
Whenthe Z·80 is in operation, the Z·80 10RQ is an output on this line.
(2)
When the LH-5803 is in operation, the LH·5803 MEl is an input on this line.
35
MREQ
"" ln/Out
(1) when the Z-80 is in operation, the Z-80 MREQ is an outpur on this line.
(2)
When the LH-5803 is in operation, the LH-5803 MEOis an input on this line.
36
RD
ln/Out
(1)
When the Z-80 is in operation, the Z-80 RD is an output on this line.
(2)
When the LH-5803 is in operation, the LH-5803 OD isan input on this line.
37 WAIT
""In
High WAIT input to the Z·80 and LH-5803.
Pulled down internally by a resistor.
38 LHA90
Out
Among the RAMs (the bank of the spacesCOOOH~ FFFFH) connected to the RAM3,
It ISan mput tc tne acoress A9 or tne R AM or EOOOH ~ F F F F H (tne stoe A 13A IS
input to CE1).
(1)
When the Z-80 is in operation, "LHA90; A9" is established.
(2)
Except that "LHA90; high" is established when the LH-5803 accesses7400H-
744FH and 7500H~754FH.
In other words, when the LH-5803 tries to access7400H -744FH and 7500H ~
754FH, it actually accesses7600H-764FH and 7700H-774FH.
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