Sharp PC-1600

PC-1600
47
GND
Power supply.
48
A8
Out Address bus (see Pin No.39l.
49 VGG
Power supply.
.
50-56 A9-A15
Out
Address bus (see Pin No.39).
57
(NC)
-
58 R/W Out
Memory write signal. With a low R/W state, the data in the CPU are sent on the data
bus.
59
Pep
Out
External latch clock. With a high state of this clock, the contents of the accumulator are
transferred onto the data bus. Use of the latch IC permits its use as the outout port (see
the ATP command).
_.-
I
60
PV
Out These are the CPU internal flip·flop output pins (PU, PV).
61
PU
Out
There are commands to set and reset PU and PV.
62
epOS
Out
The clock, in the same phase as the CPU internal basic clock, is on this line to supply
clock pu Ise to the external system.
When a 2.6MHz crvstal. is connected ac ross X LO and XL 1, a 1.3 MHz clock is supplied.
63 XLO
In
Crvstal connection pins. XLO is an input and XL1 is an output,
64 XL1
Out
Inside the CPU, the clock is divided in half. When a 2.6MHz crystal is connected, the
machine cycle within the CPU is at 1.3MHz.
65 WAIT
In
CPU wait signal. When this input is high, the CPU's internaioperation clock "ep" stops
and the CPU therefore stops executing a command. When it resumes a low state, the
CPU starts to execute a command.
Internal basic clock
.pOS
CPU operating clock
ep
I
WAIT input
I
CPU internal
I \
flip-flop WA
NOTE:
WA is the CPU internal flip-flop for WAIT. At a high to low transition of the clock
I
epOS, input of WAIT is accepted.
The CPU operating clock ep stops when WA is at high; the CPU halts a command
execution temporarily as a resu It.
66-73 IN7-INO
In
Input port. The CPU can send the signal input on the INO-I N7 to the CPU accumulator
as an 8·bit data.
It has an internal pull-up resistor. When not connected, the CPU assumes the line to
be in high impedance.
74-76
(NC)
-
NOTE: NC: No Connection
-26-