Sharp PC-1600

PC-1600
9-5. TC8576F UART pin description
The TC8578P Standard Microcomputer Interface (SMI) is a
single chip C·MOS LSI which supports the RS·232C serial
interface and Centronics compatible parallel interface, both
of wh ich are standard interfaces for microcomputers.
In the LSI is contained the RS·232C ART (Asynchronous
Receiver Transmitter), its baud rate generator, and the
Centronics transmitter/receiver interface. For the Cen-
tronics interface, either the transmitter or the receiver
mode must be selected.
When the ART receives data from the CPU, the data are
converted into serial form and sent out on the TXD line.
On the other hand, the serial data received on the RCD line
are converted into parallel form before being handed to the
CPU. The ART is able to inform the CPU at any time of
the completion of sending the data received from the
CPU or the reception of the data to be handed to the CPU.
The clock input of the IC is divided by a 4-bit program-
mable prescaler and becomes the internal clock (SYS.CLK),
which is further divided by the baud rate generator corn-
posed of a 12·bit programmable divider, for the creation of
any baud rate of 50 to 38,400 bauds.
The transmission/reception handshake pins are provided for
the Centronics parallel interface. When the 8-bit data are
received from the CPU in the transmit mode, astrobe of
the programmed pulse width is automatically issued. In the
receive mode, when data are received with astrobe singal
from the external source, a busy singal is returned to auto-
matically inform the CPU.
Pin
Symbol
ln/Out
Active
Function
No.
level
1
(NC)
-
-
Not used.
2 RD In
Low
A low on this line causes the CPU to read data or status information from the SM I.
3
WR
In
Low
A low on this line causes the SMI to receive data or control words se nt from the CPU
via the data bus.
4
CS In
Low
A lowon this line causes the SMI to be activated. When CS is at a high level, both RD
and WR are disabled.
Al AO RD WR
CS
Function
0 0 0 1 0
RX D .... data bus, serial
0 0
1
0
0
Data bus .... TX D, serial
0 1
0
1 0
PIN .... data bus, parallel
0 1 1 0 0
Data bus .... PVOUT, parallel
1 0
0
1 0
Serial status -+ data bus
1 0 1
0 0
Data bus .... parameter register
1 1
0
1 0
Parallel status -+ data bus
1 1 1
0
0
Data bus -+ command + parameter address
* *
*
*
1
Data bus, high impedance
* don't
care
* *
1 1 0
Data bus, high impedance
5.6
Al, AO In -
In combining this signal with RD or WR, the CPU selects the contents of the data
transfer with the SMI.
7
GND
Power
-
Power supply.
supply
8
INT Out
High
Logical OR of four internal signals (RXRDY, TXRDY, PRRDY, and PTRDY) which is
used to cause an interrupt to the CPU.
9-16 07-00 ln/Out -
Oata bus.
17
VCC Power
-
Power supply.
supply
18
GND Power
-
Power supply.
supply
-<.l?-