Sharp PC-1600

~o
Pin
Symbol
ln/Out
Active
Function
No.
level
10
VGG
Power supply (system's VCC input).
11
VM In
LCD backplate power supply input.
12
VDis
In
LCD backplate power supply input.
Not used by the PC-1600.
13
VA In
LCD backplate power supply input.
14 VB In
LCD backplate power supply Input.
....
15
NMI In
Non-maskable interrupt Input, A high input state causes an interrupt to the CPU.
The CPU unconditionally accepts the request and starts to execute the interrupt routine
from the address whose high order address is represented by the contents of the address
FFFCH and the low order address by the contents of FFFDH.
16
MI In
Maskable interrupt input. When the IE flag (Interrupt Enable) is set on, an interrupt
request is caused by a high M1 input state, and the CPU starts to execute the inter-
rupt routine from the address whose high order address is represented by the contents
of the address FFF8H and the low order address by the contents of FFF9H.
17 HiN In Input to the counter by which the LCD and backplate signals, HO-H7, are generated.
Normally connected to the HA pin of the CPU. With the PC·1600, this function is not
used.
18
HA
Out
CPU internal divider output through which is delivered the basic clock for the LCD
driver and connected to HIN and the segment signal generator LSI.
19
DISP Out LCD display on/off control signal outpur.
Can be set and reset by means of a command. With the PC·1600, this function is not
used.
20-27
H7-HO
Out LCD backplate signal outpur.
When the LCD is driven by the backplate signal and the segment signal, the backplate
signal is issued by the CPU.
28 OD
Out
Output disable signal. When OD is at a high level, the CPU disables the data outpur
onto the data bus for the external device. This signal is issued when writing data in the
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Memory write siqnal
29
MEO
Out
Memory enable signal. This signal is enabled to directly access the 128KB memory area;
30
MEl
Out
MEO accesses a 64KB area and MEl accesses a 64KB area.
The memory area accessible by the program counter P and stack pointer S is 64KB,
for MEO is used by the fetch and stack commands. For accessing data, both MEO
and ME1 memory areas can be accessed by the CPU command.
31-38 DO-D7
ln/Out
Bidirectional data bus which is used to write data in the external memory or to read
data from the external memory.
39-46
AO-A7
Out
Address bus which may be in three states. Goes to high impedance with the BRQ (bus
request) signal. It is possible to access the memory area of 64KB. It is also possible to
access the memory of 128KB using the MEO or ME1 signal.
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