Sharp PC-1600

PC-l600
TABLE·3
I Port address I Table·l
10Ra Addross
Oata
WR RO Operation
Ml A7
A6 A5
A4 A3 A2 Al AO 07
D6
05
04
03 02 01
00
1
1 0 0 0 0 0 0 0
0
1 Write data to FFl
0
.
Printer CR
Printer SW
Reverse
CC key
INT INT FOINT
PF key
PF key
INT
Enable Enable
Enable
INT
INT Enable
Enable
Enable
1
0
Read data f rom FF1
t
t t t t t
t
t
0
0 0 1
0 1
Reset FO
FO
(reset with "0")
Reset
1 0 Read PAO- 7 CMT
(0)
Printer
Print
FO
Reverse CC
input CR SW fNT
PF kev
PC key key
0 0 1 0
0 1
Write data to FFO CMTin
.
RMT RMT Moto,
Motor Motor Motor
(PBO- 71
Enable
OFF ON
ZO ZB ZC
ZA
1 0
Read data f rom FFE t
t
t t
t t t
t
(PBO- 7)
0 0 1 1
0 1
Write data to FFE Motor
Motor
Motor Motor
Motor Motor Motor
Motor
(PCO-7)
YD YB YC YA
XO XB
XC XA
1 0
Read data Irom FF3 t t t t t t t
t
(PCO-7)
'---
NOTE: Above are all high active as seen from the CPU side, except that FD reset is low active .
• Gate array (LR38045) pin description
Pin
Symbol
1'0
Active
Level at reset
Description
No.
level
1-8
PC7N - PCON Out
Low
High
8-bit outout port (port address: 83H).
DO - D7 correspond to PCO - 7Nvia FF3'
9 -16
PB7N - PBON
Out
Low
High
8-bit outpur port (port address: 82H).
DO - D7 correspond to PBO - 7N via FF2.
17
(NCI
18 PUl
In
(Low)
PU signal input.
[ Used for creation of a 32KS ROM signal J
19 PTI In
(High)
PT signal input.
(CSNO).
20 EZI In
(High)
ELH signal input.
21
MINI In
(High)
Ml signal input.
[ Used for creation 'of the 107N and gate
J
22
10RQ In High
10RQ signal input.
array internal enable signal.
23
MRQI
In
High
MREQ signal Input (used for generation of CSNO).
24 RSTI In
High
Reset signal input.
When the reset signal is received on this line, it issues the internal
flipflop reset signal and RSTN (2.5" FDD reset signal).
25
VCC
~ Power supplv.
26
GNO
27
IRQ
Out Low
High impedance
Interrupt signal outpur.
The output is N-channel open drain type and is pulled up to VCC
onthe PC-1600 side.
28
RONI In
Low
RO signal input.
29
WRNI In Low
WR signal Input,
I
30- 39
AOI - A71
In
Address Input.
A141. A1SI
40
(NC)
41 RSTN
Out Low Low 2.5" F DO reset signal output,
The active state of the signal is unconditionally issued with areset
signal and it must be cleared by means of software. It is also possible
to create the signal by software. (Address: 81 H, 00, WR)
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