Sharp UX-B700 - Page 72

UX-B700U
FO-B1600U
Block
Pin
Pin Name I/O Pin Description
No.
FLASH 129 D8 I/O Data 08
INTERFACE 132 D9 I/O Data 09
134 D10 I/O Data 10
137 D11 I/O Data 11
140 D12 I/O Data 12
146 D13 I/O Data 13
149 D14 I/O Data 14
152 D15 I/O Data 15
DRAM 170 DRAM_nRAS O DRAM Row Address Strobe
174 DRAM_nLCAS O DRAM Lower Column
Address Strobe
172 DRAM_nUCAS O DRAM Upper Column
Address Strobe
175 DRAM_nWE O DRAM Write Enable
177 DRAM_nOE O DRAM Output Enable
195 DRAM_A0 O DRAM Address 0
196 DRAM_A1 O DRAM Address 1
199 DRAM_A2 O DRAM Address 2
200 DRAM_A3 O DRAM Address 3
190 DRAM_A4 O DRAM Address 4
188 DRAM_A5 O DRAM Address 5
187 DRAM_A6 O DRAM Address 6
185 DRAM_A7 O DRAM Address 7
183 DRAM_A8 O DRAM Address 8
178 DRAM_A9 O DRAM Address 9
144 DRAM_D00 I/O DRAM Data 00
147 DRAM_D01 I/O DRAM Data 01
151 DRAM_D02 I/O DRAM Data 02
153 DRAM_D03 I/O DRAM Data 03
163 DRAM_D04 I/O DRAM Data 04
165 DRAM_D05 I/O DRAM Data 05
166 DRAM_D06 I/O DRAM Data 06
169 DRAM_D07 I/O DRAM Data 07
158 DRAM_D08 I/O DRAM Data 08
157 DRAM_D09 I/O DRAM Data 09
156 DRAM_D10 I/O DRAM Data 10
155 DRAM_D11 I/O DRAM Data 11
143 DRAM_D12 I/O DRAM Data 12
141 DRAM_D13 I/O DRAM Data 13
139 DRAM_D14 I/O DRAM Data 14
138 DRAM_D15 I/O DRAM Data 15
ARM 164 ARM_nRW O Not use
171 ARM_BL0 O Not use
173 ARM_BL1 O Not use
176 ARM_BL2 O Not use
179 ARM_BL3 O Not use
181 ARM_MAS0 O Not use
184 ARM_MAS1 O Not use
186 ARM_MClk O Not use
189 ARM_nM0 O Not use
192
ARM_nM1 O Not use
Hurricane (IC1) Terminal descriptions
Block
Pin
Pin Name I/O Pin Description
No.
194 ARM_nM2 O Not use
197 ARM_nM3 O Not use
198 ARM_nM4 O Not use
201 ARM_nMREQ O Not use
204 ARM_nOPC O Not use
206 ARM_nWait O Not use
RESET 40 nRESET I RESET
WATCHDOG 73 WATCHDOG O WATCHDOG
TEST PIN 29 Test1 I TEST PIN
35 Test2 I TEST PIN
37 Test3 I TEST PIN
CLK_IN
CLK_OUT
+3.3V
+2.5V
GROUND
CONTROL(1:8)
DATA(0:3)
ACLK
–CS
SCK
SDI
DCM_PWM
TDOUT
TDIN
TMODSEL
TCLK
A(0:23)
–WE
D(0:15)
–OE
–CE
TEST
–RESET
–TRESET
PCLK
SNR_CHA
SNR_CHB
PIN
SN_COVER
USB_HIGH
USB_CON
D+
D–
C(0:7)
–SLCTIN
–INIT
–STROBE
BUSY
PERROR
SLCT
–ACK
SSCG
BLOCK
OSC
48MHz
I/O
BLOCK
USB
PORT
1284
PARALLEL
PORT
PARALLEL
VDD/VSS
USB
CORE
USER
LOGIC
DRAM
I/F
–BAS
LCAS
UCAS
nOE
nWE
A(0:9)
D(0:15)
CPU CORE
ARM7TDMI
RESET
TEST
FLASH
ROM-I/F
JTAG
PORT
ANALOG
ASIC
INTERFACE
ANALOG
ASIC
PRINTHEAD
ASIC
INTERFACE
PRINTHEAD
DRIVER
ASIC
Hurricane BLOCK DIAGRAM
5 – 17
Fig. 9