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Siemens SIMATIC Box PC 820 - Interrupt Assignments

Siemens SIMATIC Box PC 820
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2-29
Box PC 820 / PC FI45 V2, Manual
A5E00051531-03
2.9 Interrupt Assignments
Interrupt Assignments
Two integral interrupt controllers of the type 82C59 handle the 16 hardware inter-
rupts (IRQ 0 to IRQ 15).
The INT output of the slave controller is connected to the IRQ 2 input of the master
controller. Interrupt 9 (IRQ 9) can be used on the bus for the assigned interrupt 2
(IRQ 2). In the initialization phase, IRQ 9 is programmed for the software interrupt
vector 0A H (IRQ 2) by the ROM-BIOS.
Priority
The interrupts are priority-scheduled in reverse number order. Interrupt IRQ 0 has
the highest priority and interrupt IRQ 7 the lowest. For triggering IRQ 2, interrupt
IRQ 8 has the highest priority and interrupt IRQ15 the lowest.
Interrupts IRQ 8 to IRQ 15 therefore have priority over interrupts IRQ 3 to IRQ 7.
The interrupt vectors are initialized and masked when the PC is powered up.
I/O Addresses of the Interrupt Controllers
Interrupt Assignment Remark Vector
SMI System management interrupt, cannot
be masked
- -
NMI Signal IO channel check 2 Fixed INT2H
IRQ 0 Timer output 0 Fixed INT8H
IRQ 1 Keyboard Fixed INT9H
IRQ 2 Cascaded (slave interrupt controller) Fixed INTAH
IRQ 3 Serial port 2 Can be switched off *) INTBH
IRQ 4 Serial port 1 Can be switched off *) INTCH
IRQ 5 Sound Vacant INTDH
IRQ 6 FD controller Can be switched off *) INTEH
IRQ 7 Parallel port 1 Can be switched off *) INTFH
IRQ 8 Real-time clock (RTC) Fixed INT70H
IRQ 9 VGA (generally not used) Vacant (AT 9 = XT 2) INT71H
IRQ 10 MPI/DP P&P **) INT72H
IRQ 11 Reserved for SafeCard on motherboard Reserved INT73H
IRQ 12 PS/2 mouse Can be switched off *) INT74H
IRQ 13 Numeric processor Fixed INT75H
IRQ 14 1st HD controller (primary) Fixed INT76H
IRQ 15 2nd HD controller (secondary) Can be switched off *) INT77H
Do not use interrupts already assigned in the system.
*) These components can be disabled via the BIOS SETUP. The functions are then no longer
available and the resources are released for other components.
**) The Onboard MPI/DP interface is Plug&Play capable, the occupied resources are managed
by the BIOS.
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