SONIX SN8P2501D - 2.2 Data Memory (RAM)

SN8P2501D
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 20 Version 1.5
2.2 DATA MEMORY (RAM)
 48 X 8-bit RAM
Address
RAM Location
BANK 0
000h
General Purpose Area
RAM Bank 0
“
“
“
02Fh
080h
System Register
080h~0FFh of Bank 0 store system
registers (128 bytes).
“
“
“
0FFh
End of Bank 0
The 48-byte general purpose RAM is separated into Bank 0. Sonix provides “Bank 0” type instructions (e.g. b0mov,
b0add, b0bts1, b0bset…) to control Bank 0 RAM directly.
2.2.1 SYSTEM REGISTER
2.2.1.1 SYSTEM REGISTER TABLE
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8
-
-
R
Z
Y
-
PFLAG
-
-
-
-
-
-
-
-
-
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B
-
-
-
-
-
-
-
-
P0M
-
-
-
-
-
-
PEDGE
C
P1W
P1M
P2M
-
-
P5M
-
-
INTRQ
INTEN
OSCM
-
WDTR
TC0R
PCL
PCH
D
P0
P1
P2
-
-
P5
-
-
T0M
T0C
TC0M
TC0C
-
-
-
STKP
E
P0UR
P1UR
P2UR
-
-
P5UR
-
@YZ
-
P1OC
-
-
-
-
-
-
F
-
-
-
-
-
-
-
-
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
2.2.1.2 SYSTEM REGISTER DESCRIPTION
R =
Working register and ROM look-up data buffer.
Y, Z =
Working, @YZ and ROM addressing register.
PFLAG =
Special flag register.
PEDGE =
P0.0 edge direction register.
INTRQ =
Interrupt request register.
INTEN =
Interrupt enable register.
WDTR =
Watchdog timer clear register.
Pn =
Port n data buffer.
PnM =
Port n input/output mode register.
OSCM =
Oscillator mode register.
PnUR =
Port n pull-up resister control register.
T0M =
T0 mode register.
PCH, PCL =
Program counter.
TC0M =
TC0 mode register.
T0C =
T0 counting register.
TC0R =
TC0 auto-reload data buffer.
TC0C =
TC0 counting register.
@YZ =
RAM YZ indirect addressing index pointer.
P1OC =
P1.0 open-drain control register.
STK0~STK3 =
Stack 0 ~ stack 3 buffer.
STKP =
Stack pointer buffer.