SONIX SN8P2501D - Tc0 Interrupt Operation

SN8P2501D
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 59 Version 1.5
6.8 TC0 INTERRUPT OPERATION
When the TC0C counter overflows, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the
TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC0IEN = 0, the trigger event TC0IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
 Example: TC0 interrupt request setup. Fcpu = 16MHz / 16.
B0BCLR
FTC0IEN
; Disable TC0 interrupt service
B0BCLR
FTC0ENB
; Disable TC0 timer
MOV
A, #20H
;
B0MOV
TC0M, A
; Set TC0 clock = Fcpu / 64
MOV
A, #64H
; Set TC0C initial value = 64H
B0MOV
TC0C, A
; Set TC0 interval = 10 ms
B0BSET
FTC0IEN
; Enable TC0 interrupt service
B0BCLR
FTC0IRQ
; Clear TC0 interrupt request flag
B0BSET
FTC0ENB
; Enable TC0 timer
B0BSET
FGIE
; Enable GIE
 Example: TC0 interrupt service routine.
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FTC0IRQ
; Check TC0IRQ
JMP
EXIT_INT
; TC0IRQ = 0, exit interrupt vector
B0BCLR
FTC0IRQ
; Reset TC0IRQ
MOV
A, #64H
B0MOV
TC0C, A
; Reset TC0C.
…
; TC0 interrupt service routine
…
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
 Note: We strongly recommend to clear TC0IRQ must be used b0bclr or bclr instructions.