SONIX SN8P2501D - 6 Interrupt; 6.1 Overview; 6.2 Inten Interrupt Enable Register

SN8P2501D
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 53 Version 1.5
6
6
6
INTERRUPT
6.1 OVERVIEW
This MCU provides three interrupt sources, including two internal interrupt (T0/TC0) and one external interrupt (INT0).
The external interrupt can wakeup the chip while the system is switched from power down mode to high-speed normal
mode. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt
request. On the contrast, when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request. All
of the interrupt request signals are stored in INTRQ register.
INTEN Interrupt Enable Register
Interrupt
Enable
Gating
INTRQ
3-Bit
Latchs
P00IRQ
T0IRQ
TC0IRQ
Interrupt Vector Address (0008H)
Global Interrupt Request Signal
INT0 Trigger
T0 Time Out
TC0 Time Out
 Note: The GIE bit must enable during all interrupt operation.
6.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
0C9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTEN
-
-
TC0IEN
T0IEN
-
-
-
P00IEN
Read/Write
-
-
R/W
R/W
-
-
-
R/W
After reset
-
-
0
0
-
-
-
0
Bit 0 P00IEN: External P0.0 interrupt (INT0) control bit.
0 = Disable INT0 interrupt function.
1 = Enable INT0 interrupt function.
Bit 4 T0IEN: T0 timer interrupt control bit.
0 = Disable T0 interrupt function.
1 = Enable T0 interrupt function.
Bit 5 TC0IEN: TC0 timer interrupt control bit.
0 = Disable TC0 interrupt function.
1 = Enable TC0 interrupt function.