SONIX SN8P2501D - Oscm Register; System Clock Measurement

SN8P2501D
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 43 Version 1.5
4.6 OSCM REGISTER
The OSCM register is an oscillator control register. It controls oscillator status, system mode.
0CAH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCM
0
0
0
CPUM1
CPUM0
CLKMD
STPHX
0
Read/Write
-
-
-
R/W
R/W
R/W
R/W
-
After reset
-
-
-
0
0
0
0
-
Bit 1 STPHX: High-speed oscillator control bit.
0 = High-speed oscillator free run.
1 = High-speed oscillator free run stop. Internal low-speed RC oscillator is still running.
Bit 2 CLKMD: System high/Low clock mode control bit.
0 = Normal (dual) mode. System clock is high clock.
1 = Slow mode. System clock is internal low clock.
Bit[4:3] CPUM[1:0]: CPU operating mode control bits.
00 = normal.
01 = sleep (power down) mode.
10 = green mode.
11 = reserved.
“STPHX” bit controls internal high speed RC type oscillator and external oscillator operations. When “STPHX=0”, the
external oscillator or internal high speed RC type oscillator active. When “STPHX=1”, the external oscillator or internal
high speed RC type oscillator are disabled. The STPHX function is depend on different high clock options to do
different controls.
 IHRC_16M: “STPHX=1” disables internal high speed RC type oscillator.
 IHRC_RTC: “STPHX=1” disables internal high speed RC type oscillator and external 32768Hz crystal.
 RC, 4M, 12M, 32K: “STPHX=1” disables external oscillator.
4.7 SYSTEM CLOCK MEASUREMENT
Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is
useful in RC mode.
 Example: Fcpu instruction cycle of external oscillator.
B0BSET
P0M.0
; Set P0.0 to be output mode for outputting Fcpu toggle signal.
@@:
B0BSET
P0.0
; Output Fcpu toggle signal in low-speed clock mode.
B0BCLR
P0.0
; Measure the Fcpu frequency by oscilloscope.
JMP
@B
 Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC
frequency.