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ST STEVAL-STWINBX1 - Figure 13. MCU and Connectivity Components (Bottom View)

ST STEVAL-STWINBX1
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Figure 13. MCU and connectivity components (bottom view)
U20: STM32U585AI ultra-low-power Arm
®
Cortex
®
-M33 with FPU and T
rustZone at 160 MHz;
U5: BlueNRG-M2SA Bluetooth
®
low energy v5.2 wireless technology module;
U7: STSAFE-A110 authentication and brand protection secure solution;
U18: STR485 3.3 V RS485 up to 20 mbps;
U23: MXCHIP EMW3080 (802.11 b/g/n compliant Wi-Fi module);
U24: ST25DV04K dynamic NFC/RFID tag IC with 64-Kbit EEPROM;
USB: USB Type-C™ connector (power supply and data);
CN4: STDC14 programming connector for STLINK-V3MINI;
SDCard: microSD card socket.
1.6.2.1 STM32U585AI
The STM32U585xx device belongs to an ultra-low-power microcontrollers family (STM32U5 series) based on the
high-performance Arm
®
Cortex
®
-M33 32-bit RISC core. They operate at a frequency of up to 160 MHz.
The Arm
®
Cortex
®
-M33 core features a single-precision FPU (floating-point unit), which supports all the Arm
®
single-precision data-processing instructions and all the data types. It also implements a full set of digital signal
processing (DSP) instructions and a memory protection unit (MPU) that enhances the application security
.
The device embeds high-speed memories (2 mbytes of Flash memory and 786 kbytes of SRAM), a flexible
external memory controller (FSMC) for static memories (for devices with packages of 90 pins and more), two
octo-SPI Flash memory interfaces (at least one quad-SPI available on all packages), an extensive range of
enhanced I/Os and peripherals connected to three APB buses, three AHB buses, and a 32-bit multi-AHB bus
matrix.
The device offers security foundation compliant with the trusted-based security architecture (TBSA) requirements
from Arm
®
. It embeds the necessary features to implement a secure boot, secure data storage, and secure
firmware update.
The device also incorporates a secure firmware installation feature that allows the customer to secure the
provisioning of the code during its production.
A flexible lifecycle is managed thanks to multiple levels of readout protection and debug unlock with password.
Firmware hardware isolation is supported thanks to securable peripherals, memories and I/Os, and privilege
configuration of peripherals and memories.
The device features several protection mechanisms for embedded Flash memory and SRAM: readout protection,
write protection, secure, and hide protection areas. They also embed several peripherals reinforcing security: a
fast AES coprocessor, a secure AES coprocessor with DPA resistance, and a hardware unique key that can be
shared by hardware with fast AES, a public key accelerator (PKA) with DPA resistance, an on-the-fly decryption
engine for octo-SPI external memories, a HASH hardware accelerator, and a true random number generator.
The device also features active tamper detection and protection against transient and environmental perturbation
attacks, thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the
PCI requirements for point of sales applications.
UM2965
Functional blocks
UM2965 - Rev 1
page 13/58

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