Dynamic Voltage scaling management
Both LDO and SMPS regulators can provide four different voltages (voltage scaling) and can operate in all Stop
modes. Both regulators also can operate in the following ranges:
• Range 1 (1.2 V, 160 MHz), high performance: provides a typical output voltage at 1.2 V. It is used when the
system clock frequency is up to 160 MHz.
• Range 2 (1.1 V, 110 MHz), medium-high performance: provides a typical output voltage at 1.1 V. It is used
when the system clock frequency is up to 110 MHz.
• Range 3 (1.0 V, 55 MHz), medium-low power: provides a typical output voltage at 1.0 V. It is used when the
system clock frequency is up to 55 MHz.
• Range 4 (0.9 V, 24 MHz), low power: provides a typical output voltage at 0.9 V. It is is used when the
system clock frequency is up to 24 MHz.
Voltage scaling is selected through the VOS[1:0] field in PWR_VOSR.
Caution: The EPOD (embedded power distribution) booster must be enabled and ready before increasing the system
clock frequency above 50 MHz in Range 1 and Range 2 (refer to document [1] for sequences to switch between
voltage scaling ranges).
2.1.6 Power supply for I/O analog switches
Some I/Os embed analog switches for both analog peripherals (ADCs, COMPs, DACs) and TSC (touch sensing
controller) functions. These switches are by default supplied by V
DDA
. However, they can be supplied by a V
DDA
voltage booster or by V
DD
, depending on the configuration of ANASWVDD and BOOSTEN bits in
SYSCFG_CFGR1.
It is recommended to supply the I/O switches with the highest voltage value between V
DDA
, V
DDA
booster,
and V
DD
.
Note: If possible, select V
DDA
or V
DDA
booster rather than V
DD
, as they are often less noisy.
The analog switches for TSC function are supplied by V
DD
.
2.2
Power supply schemes
The device is powered by a stabilized V
DD
power supply as described below:
• VDD pins must be connected to V
DD
with external decoupling capacitors: a 10 μF (typical value, 4.7 µF
minimum) single tantalum or ceramic capacitor for the package, and a 100 nF ceramic capacitor for each
VDD pin.
• VDD11 pins are present only on packages with SMPS. The SMPS step-down converter requires a 2.2 μH
(typical) external ceramic coil connected between VLXSMPS and VDD11 pins. In addition, two 2.2 μF
capacitors on VDD11 pins are connected to the VSSSMPS pin.
• The VCAP pin is present only on standard packages (without SMPS). It requires a 4.7 µF (typical) external
decoupling capacitor connected to V
SS
. If there are two VCAP pins (UFBGA169 package), each VCAP pin
must be connected to a 2.2 µF (typical) capacitor (for a total around 4.4 µF).
• The VDDA pin must be connected to two external decoupling capacitors: 100 nF ceramic and 1 μF
tantalum or ceramic.
Additional precautions can be taken to filter digital noise: VDDA can be connected to VDD through a ferrite
bead.
• The VREF+ pin can be provided by an external voltage reference. In this case, an external 100 nF + 1 μF
tantalum or ceramic capacitor must be connected on this pin.
It can also be provided internally by the VREFBUF. In this case, an external 1 μF (typical) capacitor must
be connected on this pin.
• The VBAT pin can be connected to an external battery to preserve the content of the Backup domain:
– When VDD is present, the external battery can be charged on VBAT through a 5 kΩ or 1.5 kΩ
internal resistor. In this case, the user can insert a capacitor according to the expected discharging
time (1 µF is recommended).
– If no external battery is used in the application, it is recommended to connect the VBAT pin to V
DD
with a 100 nF external ceramic decoupling capacitor.
AN5373
Power supply schemes
AN5373 - Rev 6
page 13/47
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