ST STM32U5

Contents
1 General information ...............................................................2
2 Power supply management ........................................................3
2.1 Power supplies ................................................................3
2.1.1 Independent analog peripherals supply.......................................10
2.1.2 Independent I/O supply rail ................................................11
2.1.3 Independent USB transceiver supply ........................................11
2.1.4 Battery backup domain ...................................................11
2.1.5 Voltage regulator........................................................12
2.1.6 Power supply for I/O analog switches ........................................13
2.2 Power supply schemes.........................................................13
2.3 Power supply sequence between V
DDA
, V
DDUSB
, V
DDIO2
, and V
DD
....................18
2.3.1 Power supply isolation ...................................................18
2.3.2 General requirements ....................................................18
2.3.3 Particular conditions during the power-down phase .............................18
2.4 Reset and power-supply supervisor ..............................................19
2.4.1 Brownout reset (BOR)....................................................19
2.4.2 System reset ...........................................................19
2.4.3 Backup domain reset ....................................................20
3 Packages.........................................................................21
3.1 Package summary ............................................................21
3.2 Conversion from UFBGA169 to TFBGA169 boards .................................22
3.3 Pinout summary ..............................................................23
4 Clocks............................................................................25
4.1 HSE clock....................................................................25
4.1.1 External crystal/ceramic resonator (HSE crystal) ...............................26
4.1.2 External source (HSE bypass) .............................................26
4.2 HSI16 clock ..................................................................26
4.3 MSI (MSIS and MSIK) clocks ...................................................26
4.4 LSE clock ....................................................................26
5 Boot configuration................................................................28
5.1 Boot mode selection ...........................................................28
5.2 Embedded bootloader and RSS .................................................29
6 Debug management ..............................................................30
6.1 SWJ-DP (serial-wire and JTAG debug port) .......................................30
6.2 Pinout and debug port pins .....................................................30
AN5373
Contents
AN5373 - Rev 6
page 43/47