Reset control AN3029
16/42 DocID16139 Rev 5
5.2 Hardware reset implementation
The STM8L and STM8AL do not require an external reset circuit to power-up correctly. Only
a pull-down capacitor is recommended (see
Figure 7). However, charging/discharging the
pull-down capacitor through an internal resistor has a negative influence on the device
power consumption. Therefore, the recommended capacitor value of 100 nF can be
reduced down to 10 nF to limit such power consumption.
The STM8L101xx reset state is released 1 ms after the POR value (1.35 V to 1.65 V) is
reached. At this time, V
DD
should be in the 1.65 V to 3.6 V range.
For medium density devices and medium+ and high density devices operating from 1.8 V at
power-on: the reset state is released 1 ms after the BOR minimum value (~1.75 V) is
reached.
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