ST STM8L - Schematics; Figure 10. Reference Design

Reference design AN3029
20/42 DocID16139 Rev 5
7.2 Schematics
Figure 10. Reference design
1. If these components are removed, they have to be replaced by a short connection.
2. Optional: if a separate, external reference voltage is connected on V
REF+
, the two capacitors (100 nF and 1 µF) must be
connected. V
REF+
is either connected to V
DDA
or V
REF.
3. One 100 nF Ceramic capacitor for each VDDx pin and one single 1 µF Tantalum or Ceramic capacitor.
V
DD1
V
DDA
V
REF+
V
SS 1/2 ... N
V
LCD
NRST
OSC_IN
OSC_OUT
OSC32_IN
OSC32_OUT
Biggest package
20pF
1-16MHz
0 Ohm
20pF
4
1
3 2
32.768kHz
6.8pF
6.8pF
100 μH
BEAD
1uF
1uF
Only if accurate High Speed
Oscillator is needed
1uF
OR OR
For noisy
environment
V
SS
3.6V-1.8V
(1.65V)
0 Ohm
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0OMZJGJOUFSOBM
CPPTUFSJTVTFEUP
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see note 1
External reset circuit
To power LCD
specifically
ai18711b
(see note 2)
V
DD2
V
DD3
V
DD4
10
0n
F
10
0n
F
10
0n
F
10
0n
F
(see note 3)
10
0n
F
10
0n
F
V
REF
1uF
10
0n
F
V
DD
V
SS
V
SS
V
DD
V
DD
V
SS
2.5V<V
LCD
<3.6V