BIOS Manual
5-8
- In an ECC configuration, the 82443BX asserts SERR#, for single bit (correctable) ECC errors or multiple
bit (non-correctable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any
ECC errors received during initialization should be ignored.
- The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX
initiated PCI cycle
- The 82443BX can also assert SERR# when a PCI parity error occurs during the address or data phase
- The 82443BX can assert SERR# when it detects a PCI address or data parity error on AGP
- The 82443BX can assert SERR# upon detection of access to an invalid entry in the Graphics Aperature
Translation Table
- The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of
AGP aperture and outside of main DRAM range (i.e. in the 640k - 1M range or above TOM)
- The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of
AGP aperture.
- The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX
initiated AGP cycle
PERR#
This option signals data parity errors of the PCI bus. The settings are
Enabled
or
Disabled
. Set to
Enabled
to enable the PERR# signal.
WSC# Handshake (Write Snoop Complete)
This signal is asserted active to indicate that all the snoop activity on the
CPU bus on the behalf of the last PCI-DRAM write transaction is complete
and that it is safe to send the APIC interrupt message. The settings for this
option are
Enabled
or
Disabled
. Set to
Enabled
to enable handshaking for
the WSC# signal.
USWC Write Post
The settings for this option are
Enabled
or
Disabled
. This option sets the
status of USWC (Uncacheable, Speculative, Write-Combining) posted writes
and is used to combine several partial writes to the frame buffer into a single
write in order to reduce the data bus traffic. Set to
Enabled
to enable USWC
posted writes to I/O. Set to
Disabled
to disable USWC posted writes to I/O.
BX/GX Master Latency Timer (CLKs)
This option specifies the master latency timings (in PCI clocks) for devices in
the computer. It defines the number of PCI clocks a PCI master can own on
the bus after PCI central arbiter removes the grant signal. The settings are
Disabled
,
32
,
64
,
96
,
128
,
160
,
192
or
224
.
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