Chapter 5: Running Setup
5-9
Multi-Trans Timer (Clks)
This option specifies the multi-trans latency timings (in PCI clocks) for
devices in the computer. It reduces overhead switching between different
masters. The settings are
Disabled
,
32
,
64
,
96
,
128
,
160
,
192
or
224
.
PCI1 to PCI0 Access
PCI1 refers to AGP in BX and LX chipsets. PCI0 is the normal PCI bus.
Note: Normally AGP master should not access to a PCI target
. The
settings for this option are
Enabled
or
Disabled
. Set to
Enabled
to enable
access between two different PCI buses (PCI1 and PCI0).
Memory Autosizing Support
The dynamic detection and sizing of SDRAM and EDO is performed by the
BIOS in a system populated with memory which has no SPD information.
When set to
Enable
, memory does not have the SPD information. The
settings for this option are
Auto
or
Enable
.
DRAM Integrity Mode
The settings for this option are
None
,
EC
or
ECC Hardware
.
Note: For ECC
memory only. See the table below to set the type of system memory
checking.
(Note:
New BIOS versions automatically detect setting and do
not need to be set by user.)
Setting Description
None No error checking or error reporting is done.
EC Multibit errors are detected and reported as parity
errors. Single-bit errors are corrected by the
chipset. Corrected bits of data from memory are not
written back to DRAM system memory.
ECC Multibit errors are detected and reported as parity
Hardware errors. Single-bit errors are corrected by the
chipset and are written back to DRAM system
memory. If a soft (correctable) error occurs, writing
the fixed data back to DRAM system memory will
resolve the problem. Most DRAM errors are soft
errors. If a hard (uncorrectable) error occurs, writing
the fixed data back to DRAM system memory does
not solve the problem. In this case, the second time
the error occurs in the same location, a Parity Error
is reported, indicating an uncorrectable error. If ECC
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