Tandy 1000
Technical Reference Manual
Input:
Data transfer between the 8042 and the main processor (8088) uses the inter-
rupt mode, the poll mode, or both. the 8042 interrupts the 8088 by toggling
Port
2,
Bit
4,
which
is
connected through a buffer to the 8259A interrupt con-
troller chip. The clock/calendar board uses IR3
as
an interrupt. Internally, the
8042 knows
if
the 8088 has read/written a byte from/to
it
by checking the status
of the OBF/IBF flags. Three procedures are available
to
transfer the data from
the 8042 to the 8088. They are discussed below.
Mode
1:
Full interrupt mode
This mode uses the interrupt line to signal each byte to e transmitted. As each
byte
is
transmitted, the common procedure below
is
executed except Mode
3 must have the latched interrupt cleared after each byte
is
processed. This
mode may be the fastest mode when only the clock interrupt is actively being
triggered.
Mode
2:
Initial interrupt and poll mode
This mode uses the interrupt line to signal the start of a data packet, and polls
the rest of the packet.
It
clears the latched interrupt only after
all
the data packet
is
transmitted.
it
uses the common procedure outlined below.
Mode
3:
Poll only
mode
This mode does not use the interrupt signal
at
all.
It
uses only the output register
full
flag
in
the
8042's
status register (Port 2FE).
Common procedure:
The 8088 must have the following initialized before any interrupt mode
is
used:
• A hardware interrupt vector
at
002C.
• An interrupt controller
at
port
21
(ANDed with a
F7).
The 8042 has a data packet set up in its output buffer
and
begins transmitting
by placing the
"header"
into the output register (Port 2FC). Placing the header
byte into the output register sets the output register
full
flag
in
the status register
(Port 2FE, Bit
0)
and sends a signal on the interrupt line to the 8088 (via the
8259). The 8042 begins its normal processing cycle, testing the output register
full
flag on each cycle.
If
the flag
is
set,
the 8042 sends another signal
on
the interrupt line. If the flag
is
cleared and the packet still continues to send, the 8042 places the next data
byte into the output register and sends a signal on the interrupt line to the 8088.
If the flag is cleared and the data packet is empty, the 8042 does NOT send
an
interrupt signal, but continues with its normal processing.
96
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