Tandy 1000
Technical Reference Manual
Introduction to the Video System Logic
The Video System Logic
is
composed of three functional sections: Video
Address Generation, Video Memory, and Video Data Processing.
The
Video Address Generation logic
is
composed
of
the MC6845, one control
register U99, and
six
multiplexers.
The
MC6845 generates the video addresses
and video timing signals for
all
modes of operation.
The
control register
is
used
for paging the 128K system memory. The MC6845 has a maximum address
range of 32K. Since the Video/System
RAM
size
is
128K, the
RAM
is
divided
into 4 pages
of
32K each. Selection of the page
is
determined by the Page
Register U99, by the Page Multiplexer U89, U90, and
by
associated gates.
The CPU has the option
of
addressing the
RAM
at
two different locations, one
as
32K window starting
at
88000 or
as
System
RAM
at
an
assigned 128K page
between 00000 and
AOOOO.
The top two bits
of
the control register U99 are
used to select different addressing modes for high resolution graphics. For
programming ease, any
of
the graphics modes requiring only 16K
of
memory
will
be automatically selected by the addressing logic. Multiplexers U?2 through
U?5 are used to select either the
CPU
or the video address and to switch
between row and column addresses for the dynamic
RAM
chips.
The Video Memory
is
composed
of
two 8 bit rows
of
64K dynamic RAMs (64K
x 8 x
2)
that
is
shared by the video and the
CPU
(8088).
The
video system
sees the memory organized
as
64K x 16 bits wide to allow a high video bit
rate.
See
the
RAM
Timing Chart (page
41)
for the
RAM
specifications. The
CPU sees the memory
as
only 8 bits wide. During any read operation (either
CPU or video), both banks of memory are accessed
at
the same time. The
data
is
latched into U35 and U56 for the video or into U36 and U5? for the
CPU.
The
video uses
all
16 bits
of
memory; however, the CPU expects only
8 bits, and the extra bits are ignored.
The
CPU
selects the 64K x 8 bank using
address 00000;
so
the memory
is
organized
as
128K x 8 to the
CPU.
The
RAM
is
located
at
an
address determined by the memory configuration
control port.
In
a 128K system that address
is
normally 00000 - 1
FFFF.
In
addition this memory may be accessed
at
the 32K byte address from 88000
- 8FFFF. A page register selects which of the 4 pages are available to the
CPU. The
CPU
access
is
synchronized to the video
so
that no adverse effects
are observed
at
any time.
The processor can address any location
in
memory while the video
is
using
only a 16K or 32K page. This allows one video page
to
be displayed while
another
is
being changed by the CPU. Therefore, the displayed page can be
switched during vertical retrace. A video system memory map
is
shown on
the next page.
38
To Next Page
Loading...
Need help?
General
