Tandy 1000
System Control Signal Generation
Technical Reference Manual
The
System
Control
Signal
Generator provides
the
timing strobes required
by the system. These include 10W*, 10R*, MEMW*, MEMR*, ALE,
DEN
* and
10/M
*.
These
signals
are
synthesized by U46
(IFL)
from
timing
signals A,B,C,D, 8088 status signals SSO*, DT/R*, 10/M* plus HLDA
and INTCS* (8259 chip select). Timing signals
A,
B,
C,
0 come from
flip-flops U23 and U47.
The
timing clock
is
CPUCLOCK. A
CPU
cycle
is
divided into five periods:
T1,
T2,
T3,
TWAIT,
and
T4.
Each cycle
has a clock rising edge and a clock falling edge. Thus
T1
+ denotes
rising,
and
T1
- denotes
falling.
Signal
"A"
is
started by
ALE
true
(T1
+)
and stopped by
"C",
(T2
+). Signal
"B"
is
started by
"A"
and
(T1
-)
and stopped by CPUREADY, and
"0".
Signal
"C"
is
started by
"B",
(T2+)
and stopped by "BNOT", (T3+). Signal
"0"
is
started by
"C",
(T2
-)
and stopped by "CNOT",
(T3
-).
Characteristically,
"A"
is
always
one
clock long while
"B",
"C"
and
"0"
are
variable
in
length depending
on
the number of inserted "wait"
states.
Thus any half-clock period
between
T1
+ and
T3
- can
be
logically combined
to
create the output
timing signals. See Figure
5.
All
external devices, except the 8259A Interrupt Controller, are buffered by
an
LS244 that
is
controlled by
the
DEN
*
signal.
Since
the 8259A
is
not
buffered,
the
DEN * signal must remain inactive during accesses to the 8259A.
Bus Specification
Specifications for the bus
will
include the expansion connector pin/signal
assignments and the signal characteristics.
Refer
to
the
Expansion
I/F
Connector
diagram.
See
Figure
6.
24
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