Tandy 1000
Technical Reference Manual
the bus signals
OSC
(14 MHz), (4.77 MHz) and main logic signal D2CLK (2.385
MHz). (See the Bus Interface Specification)
The RESET signals (CPURESET, SYSRST*, RST*) originate
at
U45 (8284)
which synchronizes the input
RES
*.
RES
* originates from C26 which
is
shorted
to 0 volts by either the manual reset switch or by diode CR6 when the power
is
off.
The
READY circuit synchronizes the system "ready" signals with the CPU clock
and generates the CPU input CPUREADY.
If
a function needs one or more
"wait"
states added to its access,
it
must set the READY line low. From the
main logic board, READY
is
set low by the sound
IC
for 32 extra "wait states"
and the video/system memory sets READY low for typically one or two "wait"
cycles. The READY circuit of the 8284 (U45)
is
operated
in
the non-
asynchronous mode; i.e. two sequential edges of clock
(a
rising edge first)
are required to set the CPUREADY signal true. Of the four inputs provided,
two are used, RDY2 and AEN2. Inputs to RDY2 must be high and the input
to AEN2 must be low to set CPUREADY high. Only one input
is
applied to
AEN2: 10WAIT which
is
a positive pulse generating one
"wait"
state for every
I/O cycle. The signal READY applied to the RDY2 input comes directly from
the BUS and
is
the wired-or (logical
OR)
of any/all READY's from the subsystems
which need
"wait
state(s)" inserted. READY
is
pulled-up by R34.
Oscillator Timing and Dynamic
RAM
Control
The main system timing starts with the 28.63636 MHz oscillator. This oscillator
is
a single package which produces a TTL output. From the oscillator, U39
divides the master frequency into 4 multiples. The timing diagram (Figure
4)
shows this division. 14.31818 MHz
is
used to clock the video array chip, and
also
is
used by the Intel 8284 to generate the CPU clock signal.
The first three outputs from the counter (U39) are used to derive 8 time states,
(U38) and the last output
is
used to effectively double the number to
16.
These
16 time states are shown
at
the bottom of Figure 6.1. These time states are
then used
as
J-K inputs for
F1
09 flip-flops, which generate the system timing
signals RAS*, CAS* and MUX.
The
timing diagram shows
RAS
* and
CAS
*
as
constantly occuring pulses which
cycle every 279
ns.
Only the
RAS
* and CAS * pulses for the video cycles are
constant. During the CPU cycle, RAS* and CAS* pulse will occur only
if
the
CPU
is
accessing memory. This function
is
controlled
by
U116 and
V2
of U94.
A CPU request for accesses
is
first latched by the first half of U116. As soon
as
the next CPU cycle time starts, the second half of U116
is
clocked and the
CPU access cycle starts. The CPU cycle lasts until the rising edge of
RAS
*
in the video cycle.
The
other signals generated by the system timing
are
STIS,
DYMU, and CPUL
T.
ST15
is
a syncronization signal for the Video Array chip, and references time
state 0 from U39. DYMUX occurs on the rising edge of MUX in the CPU cycle
and latches the video data. The final signal, CPULT occurs only during a CPU
access and
is
used to latch read data for the CPU.
18
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