Tandy 1000
Bus Interface
Technical Reference Manual
The interface to the main bus
is
divided into three parts: address/control strobes,
memory
data
and
I/O data. The address/control
strobe
part (BAO -
BA
19,
BMEMR
*,
BMEMW*,
BIOR *,
BIOW*)
is shared
by
both the I/O
and
the
memory
sections. Input buffers are U59,
U60
and
U42.
One
function of the
address
bus
is
the
select logic for each of the functions.
U80
decodes
all the
I/O
chip
selects
except
those for the Video/System
Memory
I/O ports which
are
decoded
by
U103. The
memory
selects are
decoded
by
U53. The I/O data
transceiver is
U97
with its output enable
decoded
by
U80. The
memory
transceiver is
U14
and
its output enable
is
decoded
by
U53. The direction con-
trol for both data transceivers are the
"read"
strobes; 10R* for U97 and
MEMR-
FOR U14.
Keyboard I Timer I Sound Circuits
The focal point for this circuit is the
8255
Programmable
Peripheral Interface
(PPI). It has three 8 bit parallel ports, A,
Band
C.
Port A is
configured
as an
input port
and
is used for
keyboard
data. Port B is
configured
as an
output
port
and
is used for control signals for the
sound,
keyboard
and
timer func-
tions. Port C is split into 4 inputs, including
the
timer
channel and #2 monitor
and
4 outputs including the keyboard/multifunction interface signals. See
Figure
8.
Keyboard Data
The
computer
receives
data
from the
keyboard
in
an
asynchronous
serial for-
mat
with
one
8 bit
word
for each keystroke. This serial
data
is converted
by
the shift register, U91. This byte is then read
by
the
CPU
through
the
8255
Port A.
On
receipt of a character an interrupt is set
and
the
keyboard
"BUSY"
signal disables further transfers from the keyboard
(112
of U104). To enable the
keyboard again, the
"keyboard
clear" signal from
8255
Port B must be toggled.
This signal
when
high clears the interrupt, the shift register
and
holds
"BUSY"
active
(U78
pin 11.)
Holding
"BUSY"
active
prevents
another
character from
being sent until the clear routine is complete. The serial data from the keyboard
consists of a
clock
signal
and
a data signal. The
clock
consists of 8 consecutive
positive pulses (signal normal state is
logic
low). The rising
edge
of each pulse
is
centered
in the
middle
of each
data
period. The
data
signal consists of 8
data
periods
and
a
"end-of-character"
bit.
Normal
state of
the
data signal is
logic
high
which represents a logic
1.
Thus
the
data
signal will
change
only
if the
data
bit is a
O.
The ninth
and
last
data
bit is
always
a
O.
In
the absence
of a ninth clock
it
will strobe a 1 into U104 and set the interrupt and busy signals.
See
the
Keyboard
Timing Chart in
the
Keyboard
Chapter.
29
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