Tandy 1000 Technical Reference Manual
The third section of the video (Video Data Processing)
is
composed of only
one 40-pin
IC.
However, a large amount of logic has been compressed into
that single HCMOS custom
IC.
Figure 13 shows a block diagram of the logic.
The multiplexed data input from the
RAM
is
divided back into 16 bits of infor-
mation. For the alphanumeric mode this
is
character byte and attribute byte
data.
In
alphanumeric mode, the character data
is
used to address the character
ROM. The character ROM output
is
loaded into a shift register controls the
on/off selection of each video dot. The attribute byte defines foreground and
background color.
In
graphics mode, the data bits are first rearranged depen-
ding on the mode, and then loaded into the shift register.
The
mode selection
multiplexer selects alpha, 2 color, 4 color medium resolution, 4 color high resolu-
tion, or 16 color modes. The output of the mode selection multiplexer clocks
the
RGBI
data before
it
goes to the palette
RAM
and then clocks
it
again after
the palette. From this last register, the
RGBI
data passes through the border
color mux and then through the output buffers
as
RGBI data. The
RGB
out-
puts are also used to generate the composite color signal.
The remaining logic of the Video Array consists of the timing logic, the control
register logic and the timing delay logic. The timing logic provides the clocks
and shift load signals for the latches and the shift registers. The control registers
are loaded by the system software and provide the mode selection and color
control bits. The timing delay logic synchronizes
all
the logic. See Figure 14
for the Video Array Block Diagram.
40
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