Tandy 1000 Technical Reference Manual

Tandy 1000 Technical Reference Manual
PIN
NUMBER PIN NAME
SYMBOL FUNCTION
DO·D7 3·state input/output lines. Bi·directional Com·
munication lines between WD8250 and Data Bus.
All assembled data TX and RX, control words, and
status information are transferred via the DO-D7
data bus
RCLK This input is the 16X baud rate clock for the
receiver section of the chip (may be tied to
BAUDOUT pin 15)
SIN
Received Serial Data In from the communications
link (Peripheral device, modem or data set).
SOUT
Transmitted Serial Data Oul to the communication
link. The SOUT signal is set to a (logic 1) marking
condition upon a MASTER RESET
CSO When CSO and CSl are high, and CS2 is low, chip
CSl is selected Selection is complete when the ad·
CS2
dress strobe ADS latches the chip select signals.
RECEIVECLK
10
SERIAL INPUT
11
SERIAL OUTPUT
12
CHIPSELECT
13
CHIPSELECT
14
CHIP SELECT
15 BAUDOUT
BAUDOlJT 16X clock signal for the transmitter section of the
WD8250. The
clock rate is equal to the oscillator
frequency divided by the divisor loaded into the
divisor latches. The BAUDOUT signal may be used
to clock the receiver by tying to (pin 9) RCLK.
16 EXTERNAL
CLOCK IN XTAL 1 These pins connect the crystal or signal clock to
17 EXTERNALCLOCKOUT XTAL2 the WD8250 baud rate divisor circuit.
1·8 DATA BUS
18
19
20
21
22
23
24
25
DATA OUT STROBE
DATA OUT STROBE
GROUND
DATA IN STROBE
DATA IN STROBE
DRIVER DISABLE
CHIP SELECT OUT
ADDRESS STROBE
DOSTR
DOSTR
VSS
DISTR
DISTR
DDIS
CSOUT
When the chip has been selected, a low DOSTR or
high DOSTR will latch data into the selected
WD8250 register (a CPU write). Only one of these
lines need be used. Tie unused line to its inactive
state. DOSTR - high or DOSTR - low.
System signal ground
When chip has been selected, a low DISTR or high
DISTR
will allow a read of the selected WD8250
register (a CPU read). Only one of these lines need
be used. Tie unused line to its inactive state.
DiSii'l - high or DISTR - low.
Output goes low whenever data is being read from
the WD8250. Can be used to reverse data direction
of external transceiver.
Output goes high when chip is selected. No data
transfer can be initiated until CSOUT is high
When low, provides latching for register. Select
(AO, A 1, A2) and chip select (CSO, CS1, CS2)
NOTE: An active ADS signal is required when the
Register Select (AO, A 1, A2) signals are not stable
for the duration of a read or write operation. If nol
required, the Arm input can be tied permanently
low
26 REGISTER SELECT A2
A2
27 REGISTER SELECT A1
Al
28 REGISTER SELECT AO
AO
29
NO CONNECT
NC
30 INTERRUPT
INTRPT
31 OUTPUT 2
OUT2
32 REQUEST TO
SEND
RTS
33 DATA
TERMINAL
DTR
READY
34 OUTPUT 1
OUT1
35
MASTER RESET
MR
36
CLEAR TO SEND CTS
37
DATA SET READY DSR
38
RECEIVED LINE
RSLD
SIGNAL DETECT
39
RING
INDICATOR
Ai
40
+5V
VCC
These three inputs are used to select a WD8250
internal register during a data read or write.
NoConnect
Output goes high whenever an enabled interrupt
is pending.
User-designated output that can be programmed
by Bit ;LQ!... the modem control register = 1,
causes OUT2 to go low.
Output when low informs the modem or data set
that the WD8250 is ready to transmit data.
Output when low informs the modem or data sel
that the WD8250 is ready to communicate.
1 causes OUT1 to go low.
When high clears the registers to states
Input from DCE indicating remote device is ready
to transmit.
Input from DCE used to indicate the status of the
local data set.
Input from DCE indicating that it is receiving a
signal which meets its signal quality conditions.
Input, when low, indicates that a ringing signal is
being received by the modem or data set.
+ 5
Volt Supply.
Figure 16
79

Tandy 1000 Specifications

General

Processor	Intel 8088
Processor Speed	4.77 MHz
RAM	128 KB (expandable to 640 KB)
Operating System	MS-DOS 2.11
Manufacturer	Tandy Corporation
Release Year	1984
Storage	Single or double 5.25" floppy disk drive (360 KB), optional hard drive
Sound	Tandy 3-voice sound
Ports	Parallel, Serial
Graphics	CGA (Color Graphics Adapter)
Graphics Modes	320x200, 640x200