BIT VALUE SYMBOL DESCRIPTION
0 1 CV “1” = constant voltage operation
1 2 CC “1” = constant current operation
2 4 NFLT “1” = No fault, is set when all faults cleared
3 8 0 Not used
4 16 AST “1” = Auto start is enabled
5 32 FBE “1” = Foldback protection is enabled
6 64 0 Not used
7 128 LOC “1” = Local mode, “0” = Remote mode
8 to 15 0 0 Not used
Syntax:
*ESR ?
Response: <nnn>, a number from 0 to 255
Example:
32 (an illegal command was received)
11.8.8. Set the Standard Event Status Enable Register
When one or more bits in the Standard Event Status Event Register (*ESR, see above) are set, a bit can be
set in the Status Byte (*STB,see section 11.8.5). This is done by setting bits in the enable register.
Syntax:
*ESE <nnn>
Parameter: <nnn> is a number from 0 to 255. The bit assignments are the
same as the
*ESR, in the table above
Example:
*ESE 60 will cause bit 5 in the Status Byte to be set if there is a
query error, fault shut-down, execution error or a command error
Query:
*ESE? will return 60 in the example
11.8.9. Enable the Operation Complete
This command will cause bit 0 of the Standard Event Status Register to go to
1 when all pending commands
are completed. Because of the Genesys™ power supply architecture, this bit will go to
1 when the *OPC is
received, even if the output is in transition because of a prior command
Syntax:
*OPC
11.8.10. Read the Operation Complete
This query will read back if all pending operations are completed. This query will always return
1, even if
the DC output is in transition because of a prior command
Syntax:
*OPC ?
THE SCPI ERROR AND STATUS REGISTERS
11.8.11. Read the Operational Condition Condition Register
This register reports several operating modes and settings of the power supply. Although separate SCPI
commands may also report this information, the register is beneficial because it may allow any brief mode
change to be latched into an event register for later reading
This is a conditional register. The bits are set to “1” when the mode occurs and cleared when the mode
turns off. The values are read-only.
These are the bit assignments of the Operational Condition Condition Register:
50
To Next Page
Loading...
