EDC_SYNCx_OUT
3
2
6
5
1
4
EDIO_DATA_IN[7:0]
EDIO_LATCH_IN
3
2
6
5
1
4
EDIO_DATA_IN[7:0]
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SPRS717H –OCTOBER 2011–REVISED MAY 2015
Table 7-98. PRU-ICSS ECAT Timing Requirements – Input Validated with LATCH_IN (continued)
(see Figure 7-102)
NO. MIN MAX UNIT
6 t
r(EDIO_DATA_IN)
Rising time, EDIO_DATA_IN 1.00 3.00 ns
t
f(EDIO_DATA_IN)
Falling time, EDIO_DATA_IN 1.00 3.00 ns
Figure 7-102. PRU-ICSS ECAT Input Validated with LATCH_IN Timing
Table 7-99. PRU-ICSS ECAT Timing Requirements – Input Validated with SYNCx
(see Figure 7-103)
NO. MIN MAX UNIT
1 t
w(EDC_SYNCx_OUT)
Pulse width, EDC_SYNCx_OUT 100.00 ns
2 t
r(EDC_SYNCx_OUT)
Rising time, EDC_SYNCx_OUT 1.00 3.00 ns
3 t
f(EDC_SYNCx_OUT)
Falling time, EDC_SYNCx_OUT 1.00 3.00 ns
4 t
su(EDIO_DATA_IN-
Setup time, EDIO_DATA_IN valid before 20.00 ns
EDC_SYNCx_OUT)
EDC_SYNCx_OUT active edge
5 t
h(EDC_SYNCx_OUT-
Hold time, EDIO_DATA_IN valid after EDC_SYNCx_OUT 20.00 ns
EDIO_DATA_IN)
active edge
6 t
r(EDIO_DATA_IN)
Rising time, EDIO_DATA_IN 1.00 3.00 ns
t
f(EDIO_DATA_IN)
Falling time, EDIO_DATA_IN 1.00 3.00 ns
Figure 7-103. PRU-ICSS ECAT Input Validated With SYNCx Timing
Copyright © 2011–2015, Texas Instruments Incorporated Peripheral Information and Timings 227
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