AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
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Table 4-1. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET BUFFER PULLUP
ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS
PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13]
NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10]
[7] (mA) [11] [12]
NA A14 MCASP0_AHCLKX mcasp0_ahclkx 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP0_strobe 1 I/O
mcasp0_axr3 2 I/O
mcasp1_axr1 3 I/O
EMU4 4 I/O
pr1_pru0_pru_r30_7 5 O
pr1_pru0_pru_r31_7 6 I
gpio3_21 7 I/O
NA A13 MCASP0_ACLKX mcasp0_aclkx 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0A 1 O
spi1_sclk 3 I/O
mmc0_sdcd 4 I
pr1_pru0_pru_r30_0 5 O
pr1_pru0_pru_r31_0 6 I
gpio3_14 7 I/O
NA C13 MCASP0_FSR mcasp0_fsr 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP0B_in 1 I
mcasp0_axr3 2 I/O
mcasp1_fsx 3 I/O
EMU2 4 I/O
pr1_pru0_pru_r30_5 5 O
pr1_pru0_pru_r31_5 6 I
gpio3_19 7 I/O
NA D12 MCASP0_AXR0 mcasp0_axr0 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0_tripzone_input 1 I
spi1_d1 3 I/O
mmc2_sdcd 4 I
pr1_pru0_pru_r30_2 5 O
pr1_pru0_pru_r31_2 6 I
gpio3_16 7 I/O
NA D13 MCASP0_AXR1 mcasp0_axr1 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP0_index 1 I/O
mcasp1_axr0 3 I/O
EMU3 4 I/O
pr1_pru0_pru_r30_6 5 O
pr1_pru0_pru_r31_6 6 I
gpio3_20 7 I/O
36 Terminal Configuration and Functions Copyright © 2011–2015, Texas Instruments Incorporated
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