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SPRS717H –OCTOBER 2011–REVISED MAY 2015
Table 4-1. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET BUFFER PULLUP
ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS
PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13]
NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10]
[7] (mA) [11] [12]
U7 U5 LCD_VSYNC
(7)
lcd_vsync 0 O Z L 7 VDDSHV6 / Yes 6 PU/PD LVCMOS
VDDSHV6
gpmc_a8 1 O
gpmc_a1 2 O
pr1_edio_data_in2 3 I
pr1_edio_data_out2 4 O
pr1_pru1_pru_r30_8 5 O
pr1_pru1_pru_r31_8 6 I
gpio2_22 7 I/O
NA B13 MCASP0_FSX mcasp0_fsx 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0B 1 O
spi1_d0 3 I/O
mmc1_sdcd 4 I
pr1_pru0_pru_r30_1 5 O
pr1_pru0_pru_r31_1 6 I
gpio3_15 7 I/O
NA B12 MCASP0_ACLKR mcasp0_aclkr 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP0A_in 1 I
mcasp0_axr2 2 I/O
mcasp1_aclkx 3 I/O
mmc0_sdwp 4 I
pr1_pru0_pru_r30_4 5 O
pr1_pru0_pru_r31_4 6 I
gpio3_18 7 I/O
NA C12 MCASP0_AHCLKR mcasp0_ahclkr 0 I/O L L 7 NA / VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0_synci 1 I
mcasp0_axr2 2 I/O
spi1_cs0 3 I/O
eCAP2_in_PWM2_out 4 I/O
pr1_pru0_pru_r30_3 5 O
pr1_pru0_pru_r31_3 6 I
gpio3_17 7 I/O
Copyright © 2011–2015, Texas Instruments Incorporated Terminal Configuration and Functions 35
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